Quote Originally Posted by informal View Post
Are you sure L3 in Deneb is slower than DC DDR3 ? That doesn't seem right. The L3 is in Deneb and Agena has a lot lower latency than any possible DDR3 DC configuration you can think of(think ~7ns for the L3 Vs 45ns in the bet case for OCed DDR3 DC on crack...). BW is another matter,the cores does not need that much bandwidth to begin with. Maybe with 8 BD cores we might see a limitation when all the cores are loaded in some mem. BW limited application.
I don't have the DDR-3 platform right now, but if you use Everest Memory test, you can get about 10GB/s for L3 cache on Deneb.

Quote Originally Posted by zir_blazer View Post
If anything, that statement could be easily verified by comparing Propus vs Deneb scaling at the same settings.
I think that he is talking about the fact that as Deneb Cores and Cache L3/IMC scales their Frequencies independently, by just overclocking the Cores you are demanding more bandwidth (As you can process more data) yet the Cache L3/IMC will still give you exactly the same. That is why a Propus vs Deneb comparision would be interesing to see if the Cache L3 is working as a bottleneck (Propus performing better in some instances), or if the K10 is such sensitive to memory latency that by making the Cache L3 work faster (So, reducing access latency) may have higher than expected results.
It would be the design of the L3 / IMC.

In K8 architecture, IMC directly communicates with L2 cache in each core.
The simple illustration is the CnQ-throttled CPUs have lower memory speed.

In K10 architecture, IMC communicates with L3 cache (or NB?) and the bandwidth is limited to NB frequency.