AMD embraces AVX making a new superset with SSE5(256bit support)

[informal]

Shintai ,there are about ~100 or less new instructions in AVX(new as not being previously supported by intel hw). The rest ,more than 300 legacy SSE instr. are updated for better performance on future hw(and less than 100 from those 300 are widened to 256bits to support those fp vector instructions).

BTW,SSE4a is 4(in words:four) instructions so the die space that was "wasted" is really huge(I can see AMD pulling their hair over this "wasted" space ). Two of those four(LZCNT and POPCNT) doesn't even need to be included in a SSE4 in order to be available and used.

[Shintai]

Shintai ,there are about ~100 or less new instructions in AVX(new as not being previously supported by intel hw). The rest ,more than 300 legacy SSE instr. are updated for better performance on future hw(and less than 100 from those 300 are widened to 256bits to support those fp vector instructions).

And there is 46 in SSE5.

So tell me Shintai, please tell us where is the fused multiply add acceleration in Sandy Bridge or AVX?



We're absolutely begging to know, just like the 2010 DX11 GPUs.


Running through SSE5's rectification, it looks like it has everything AVX touted, with extra few features that SSE5 had from the start.

Would be easier if you checked my links....