AMD embraces AVX making a new superset with SSE5(256bit support)

[Shintai]

*New* SSE5,the one AMD presents in the tech doc. is a superset of AVX.Whether it is supported or not is up to OS and compiler support. Remember AMD64 and EMT64 hw realizations(same but not the same on hw level-still compatible)? The fact is that AMD just matched AVX in performance by adding 4 operand instructions and 256b vectors...


He was referring to (now old) specification for 128bit media instructions/2 operand instr. support in Bulldozer versus the now released spec. of 256bit vector and 4 operand support-and this is a big difference.


PS: SSE5 notation is gone(as it seems) and AMD now calls this superset : 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions

Its very very far from AVX. And calling it a superset means it should contain all AVX. And since it contains close to nothing or actually nothing..then no.

I dont think you actually understand this. Read the paper I linked.

Something compiled for AVX and something compiled for SSE5 is 100% incompatible. SSE5 is more a catchup to SSE4 and then add a few new things that will yet again prove useless in the long run. Not because it cant be used. But simply because of lack of support like always.

AMD64 and EMT64 wasnt even fully compatible. Plus I think you fail the concept of how the technology move. You dont add it overnight or even before. Look on all the previous times. Its always a catchup scenario. And this wont change anything.