AMD embraces AVX making a new superset with SSE5(256bit support)

[Shintai]

I said that compiler support needs to be there,just as it needs to be there for AVX in order to be fully utilized(as intel designed it to). That's why AMD intros the tech doc. ~2 years before Interlagos hits the market,in order to get the necessary info out for developers and partners(an M$ is a partner and an important one). Did you forget AMD64 and who adopted who's implementation ?

BTW,original SSE5 was introduced approx. 2 years ago and in those days Interlagos(or whatever market name BD core had) was scheduled for 2009 release. We now know AMD postponed bulldozer and redesign it a bit,and we now know why they did it and what parts they redesigned(256bit support,4 operand instr.,new AVX like instructions).
Even original SSE5 with those specs promised some hefty perf. improvements versus the previous implementation,so AMD hardware will run even better with the extended instruction set when software gets coded properly for it.PGI and GCC were on board back in the 2007 with original SSE5,you can bet they will be in time Interlagos hits.

The important thing is AMD improved and matched AVX on hardware level and there are 2 years to get the developer and compiler support for it.Also it will be backwards compatible to all pre-SSE4 optimized software(which is a large majority)

SSE5 aint AVX. And AMD64 was a whole other ballgame. AMD only won because MS said F U to Intel.

Everyone and their mother uses Intel compilers. They dont use MS or AMD compilers since they are slower. And again. SSE5 got nothing to do with AVX and its not a superset. Lookup that word please.

AMD dont even have full SSE4.x support yet.

And in best case, SSE5 is a dumped down version of SSE4 with some 256bit mix.

Please read Intels AVX paper. It will save alot of posting.

SSE4A ended as what today? Wasted transistors and designtime?

SSE5 is about 170 instructions with what, 50 as 256bit? AVX is close to 400, with ~half of them being 256bit.

And you claim SSE5 is a superset of AVX? Oh thats hilarious!

SSE5 is mostly Intels SSE4 with alittle 256bit mixed in. You could say its like SSE3+SSE4A when Intel had SSE3+SSE4.1