Quote Originally Posted by Glow9 View Post
In english?
The same guy who found the pdf had this to say.

Basically, this instruction set extension allow AMD to "patch" the only two deficiencies of SSE5 (compared to AVX): 256-bit vectors and 4-operand instructions, while preserving all SSE5's (many) strengths.

In fact, looking at the instruction encoding, AMD did not intend or attempt to follow AVX. For example, AVX's 2-byte prefix format was not used, while AVX's 3-byte prefix format was used to allow access to the 4th operand and the 256-bit YMM registers.

This is IMHO an aggressive move. It is a confidence call from AMD, saying whatever we're going to do in our next generation will be better than yours (Intel's).