The stead march toward higher and higher clockspeed has reached a fundamental limit above and beyond the power wall. The ability to clock a device 'faster' depends on more than just the max power. A transistor can only clock as fast as it's ability to 'turn on', a group of transistors can only clock as fast as the ability for the cumulative circuit to reach the correct evaluation phase of the 'on' or 'off' state, again by flipping transistor states.
The steady march to more clock as asymptotically approached a flat line, with smaller and smaller incremental increases one lithography node to the next. This is driven in part by smaller gains in transistor performance each iteration, and also driven by added complexity of the circuit design (architecture/IPC).
Jack








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