Quote Originally Posted by Calmatory View Post
Depends on the architecture and bottlenecks. E.g. if AMD is able to decrease cache latencies with few minor fixes and then add more cache, this, in some situations, could yield alot higher IPC improvements than what Intel could do with their architecture which is already giving all it has without major bottlenecks. Though, this is just an example case and I am not saying that AMD could "fix the latencies" with few "minor fixes" or that lower latencies with possible bigger caches with Deneb would yield this and this much improvement over Agena.
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Caches, especially the L1 are so tightly integrated into the core that playing with their latency means redoing basically everything.
The L3 can avoid this by using a async interface.However , it's performance is only a fraction of L2 , not to mention L1.