ASUS Maximus II Formula - new P45 king?

[CryptiK]

Your settings would definitely give him more headroom, but he is already stable at 465 x 8 so I reckon trying to get him onto the 9x multi and lowering the ram to 1:1 and boosting a couple of voltages will show what his cpu's limit is.

[SiGfever]

Your settings would definitely give him more headroom, but he is already stable at 465 x 8 so I reckon trying to get him onto the 9x multi and lowering the ram to 1:1 and boosting a couple of voltages will show what his cpu's limit is.

I edited the numbers some.

[CryptiK]

Looks fine, I'd add my GTL Ref settings to that though as they do help, and your voltages are a little more aggressive, but the cpu can handle it, he just has to try it out. Not many Q66's or 67's do 3.8GHz+ without getting insane on the voltages so it might be at its limit.

[SiGfever]

Looks fine, I'd add my GTL Ref settings to that though as they do help, and your voltages are a little more aggressive, but the cpu can handle it, he just has to try it out. Not many Q66's or 67's do 3.8GHz+ without getting insane on the voltages so it might be at its limit.

I do use your GTL settings and they helped me lower my vcore and FSB.

[Darknezz]

Hello what's the highest Fsb anyone has run with 2x2Gb Bloks???

[Codeman05]

Up PL to 10 for now. 10 is lowest you can go 1:1. Maybe some more vNB will help. Also set DRAM CLK Skew to advance 250

Thanks, that was it, I'm now able to use the 1:1.
I'm booting a 1:1 with 453x9.5 = 4.3GHZ & 906DDR2 as I know this was stable on my prior board.

I can boot but I now fail Prime blend in under 5 minutes on one thread, 10ish on the second.
Looks like I'm hitting another FSB wall. 477x9 w/ 1:1 fails in about 3 seconds.

Bios Settings

How high can I go "safely" on the FSB Term & vNB?
Or do I need to loosen up the memory even though it is running slower?

Thanks guys, sorry for the questions, my first Intel chipset since the NF2

[CryptiK]

Thanks, that was it, I'm now able to use the 1:1.
I'm booting a 1:1 with 453x9.5 = 4.3GHZ & 906DDR2

I know these settings were easily stable on the 780i, but I now fail Prime blend in under 5 minutes on one thread, 10ish on the second.
Looks like I'm hitting another FSB wall.

Bios Settings

How high can I go "safely" on the FSB Term & vNB?
Or do I need to loosen up the memory even though it is running slower?

Thanks guys, sorry for the questions, my first Intel chipset since the NF2

Your ram should be ok as it is, and your vNB shouldnt need to go higher for chipset stability.

Try +60/+10/+60/+10 on the GTL refs, and enable load line calibration. I'd also drop that vFSB to ~1.3v you shouldnt need 1.4v.

Hello what's the highest Fsb anyone has run with 2x2Gb Bloks???

FSB is not really relevant regarding memory module size, if your 2 x 2GB ram does 550 MHz, your could run 550 FSB.

[Codeman05]

Your ram should be ok as it is, and your vNB shouldnt need to go higher for chipset stability.

Try +60/+10/+60/+10 on the GTL refs, and enable load line calibration. I'd also drop that vFSB to ~1.3v you shouldnt need 1.4v.

Well that helped slightly, but still the first thread fails within 6 minutes.
Think I just got a bad draw on this board? I know the cpu & ddr are good for these speeds, just seems like the mobo isn't keeping up.

Here are the current settings after your recommendations:

Ai Overclock Tuner: Manual
OC From CPU Level Up: Auto
Ratio CMOS Setting: 9.5
FSB Frequency: 453
CPU Clock Skew: Normal
NB Clock Skew: Normal
FSB Strap to North Bridge: 400
DRAM Frequency: DDR2-906Mhz
DRAM CLK Skew on Channel A1: Advance 250
DRAM CLK Skew on Channel A2: Advance 250
DRAM CLK Skew on Channel B1: Advance 250
DRAM CLK Skew on Channel B2: Advance 250
DRAM Timing Control: Manual

1st Information:

CAS# Latency: 5 DRAM Clocks
DRAM RAS# to CAS# Delay: 5 DRAM Clocks
DRAM RAS# Precharge: 5 DRAM Clocks
DRAM RAS# Activate to Precharge: 18 DRAM Clocks
RAS# to RAS# Delay: 5
Row Refresh Recycle Time: 60 
Write Recovery Time: 6
Read to Precharge Time: 5

2nd Information:

Read to Write Delay (S/D): 10
Write to Read Delay (S): 4
Write to Read Delay (D): 5
Read to Read Delay (S): 6
Read to Read Delay (D): 6
Write to Write Delay (S): 5
Write to Write Delay (D): 6

3rd Information:

Write to PRE Delay: 16
Read to PRE Delay: 6
PRE to PRE Delay: 1
All PRE to ACT Delay: 6
All PRE to REF Delay: 6
DRAM Static Read Control: Disabled
DRAM Read Training: Disabled
MEM. OC Charger: Enabled
Ai Clock Twister: Moderate
Ai Transaction Booster: Manual

Common Performance Level: 10
Pull-in of CHA PH1: Disabled
Pull-in of CHA PH2: Disabled
Pull-in of CHA PH3: Disabled
Pull-in of CHB PH1: Disabled
Pull-in of CHB PH2: Disabled
Pull-in of CHB PH3: Disabled

PCIE Frequency: 100

CPU Voltage: 1.325
CPU PLL Voltage: 1.50
FSB Termination Voltage: 1.45
DRAM Voltage: 2.2
North Bridge Voltage: 1.30
South Bridge 1.5 Voltage: 1.50
South Bridge 1.1 Voltage: 1.10

CPU GTL Reference (0): +60
CPU GTL Reference (1): +10
CPU GTL Reference (2): +60
CPU GTL Reference (3): +10
NB GTL Reference: Auto
DDR2 ChA Reference Voltage: Auto
DDR2 ChB Reference Voltage: Auto
North Bridge DDR Reference: Auto

CPU Configuration:

Ratio CMOS Setting: 9.5
C1E Support: Disabled
Max CPUID Value Limit: Disabled
Intel Virtualization Tech: Disabled
Execute Disable Bit: Disabled

Load-Line Calibration: Enabled
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled

Thanks again

[Codeman05]

Well I raising my CPL from 10 to 12...now Priming for 20 mins....certainly not long enough to say its rock stable, but that does appear to have taken me past this little FSB wall that failed in under 5.

Will keep you posted, going to start trying for 4.5GHz now

[CryptiK]

OK, give it more vNB - try 1.4 vNB and PL10 again. Also increase you vcore to ~1.35v in bios.

[Darknezz]

My probelem is that my computer freezes up en windows when i Have the Fsb at 530 and the ram are running at 1066mhz but run Prime95 for 6 hours no freeze op just when i use explorer..?? Need some settings. Ram are 2x2Gb PC2-8500 Vitesta Extreme Edition

CPU Voltage:
CPU PLL Voltage:
FSB Termination Voltage:
DRAM Voltage:
North Bridge Voltage:
South Bridge 1.5 Voltage:
South Bridge 1.1 Voltage:

Or what ever need tunning..

[psygnosi]

Hi Cryptik,

I have these settings currently on my system and IBT gets 10 passes and prime95quad passes for 12 Hours. I need help tweaking the GTLs. I'm not sure I if I did the calculations correctly. Thanks in advance.

Psygnosi

4.0Ghz (8.5 x 470)
Processor: Q9550 E0 FPO/Batch L827A932 S-Spec SLB8V

Extreme Tweaker
Ai Overclock Tuner : Manual
OC From CPU Level Up : Auto
CPU Ratio Control : Manual
- Ratio CMOS Setting : 8.5
FSB Frequency : 470
CPU Clock Skew : Auto
North Bridge Clock Skew : Auto
FSB Strap to North Bridge : Auto
DRAM Frequency: DDR2-940MHz
Dram Clock Skew CH1 A1 : Auto
DRAM Clock Skew CH1 A2 : Auto
Dram Clock Skew CH1 B1 : Auto
Dram Clock Skew CH1 B2 : Auto


DRAM Timing Control: Manual
CAS# Latency : 5
RAS# to CAS# Delay : 5
RAS# Precharge : 5
RAS# ActivateTime : 15
RAS# to RAS# Delay : Auto
Row Refresh Cycle Time : Auto
Write Recovery Time : Auto
Read to Precharge Time : Auto

Read to Write Delay (S/D) : Auto
Write to Read Delay (S) : Auto
Write to Read Delay (D) : Auto
Read to Read Delay (S) : Auto
Read to Read Delay (D) : Auto
Write to Write Delay (S) : Auto
Write to Write Delay (D) : Auto

Write to PRE Delay : Auto
Read to PRE Delay : Auto
PRE to PRE Delay : Auto
ALL PRE to ACT Delay : Auto
ALL PRE to REF Delay : Auto

DRAM Static Read Control: Disabled
Dram Read Training : Disabled
MEM OC Charger : Enabled
Ai Clock Twister : Auto
Transaction Booster : Manual

Common Performance Level [10]

Pull-In of CHA PH1 Enabled
Pull-In of CHA PH2 Enabled
Pull-In of CHA PH3 Enabled
Pull-In of CHA PH4 Enabled
Pull-In of CHA PH5 Enabled
Pull-In of CHB PH1 Enabled
Pull-In of CHB PH2 Enabled
Pull-In of CHB PH3 Enabled
Pull-In of CHB PH4 Enabled
Pull-In of CHB PH5 Enabled

PCIE Frequency : 100

CPU Voltage : 1.39
CPU PLL Voltage : 1.56
FSBT : 1.25
DRAM Voltage : 1.9
North Bridge Voltage : 1.25
South Bridge Voltage 1.5 : 1.5
South Bridge Voltage 1.1 : 1.10

CPU GTL Reference 0 : Auto
CPU GTL Reference 1 : -40mv
CPU GTL Reference 2 : Auto
CPU GTL Reference 3 : -40mv
North Bridge GTL Reference : Auto
DDR2 Channel A REF Voltage : Auto
DDR2 Channel B REF Voltage : Auto
North Bridge DDR Reference : Auto

Load Line Calibration : Enabled
CPU Spread Spectrum : Disabled
PCIE Spread Spectrum : Disabled

[CryptiK]

My probelem is that my computer freezes up en windows when i Have the Fsb at 530 and the ram are running at 1066mhz but run Prime95 for 6 hours no freeze op just when i use explorer..?? Need some settings. Ram are 2x2Gb PC2-8500 Vitesta Extreme Edition

CPU Voltage:
CPU PLL Voltage:
FSB Termination Voltage:
DRAM Voltage:
North Bridge Voltage:
South Bridge 1.5 Voltage:
South Bridge 1.1 Voltage:

Or what ever need tunning..

What vdimm are you currently running? Can you pass Prime95 large FFT and 5 - 10 passes of linpack? Is the ram memtest stable? You should be at about 1.3 - 1.35 vNB for 530 FSB stable.

Hi Cryptik,

I have these settings currently on my system and IBT gets 10 passes and prime95quad passes for 12 Hours. I need help tweaking the GTLs. I'm not sure I if I did the calculations correctly. Thanks in advance.

Psygnosi

4.0Ghz (8.5 x 470)
Processor: Q9550 E0 FPO/Batch L827A932 S-Spec SLB8V

Extreme Tweaker
Ai Overclock Tuner : Manual
OC From CPU Level Up : Auto
CPU Ratio Control : Manual
- Ratio CMOS Setting : 8.5
FSB Frequency : 470
CPU Clock Skew : Auto
North Bridge Clock Skew : Auto
FSB Strap to North Bridge : Auto
DRAM Frequency: DDR2-940MHz
Dram Clock Skew CH1 A1 : Auto
DRAM Clock Skew CH1 A2 : Auto
Dram Clock Skew CH1 B1 : Auto
Dram Clock Skew CH1 B2 : Auto


DRAM Timing Control: Manual
CAS# Latency : 5
RAS# to CAS# Delay : 5
RAS# Precharge : 5
RAS# ActivateTime : 15
RAS# to RAS# Delay : Auto
Row Refresh Cycle Time : Auto
Write Recovery Time : Auto
Read to Precharge Time : Auto

Read to Write Delay (S/D) : Auto
Write to Read Delay (S) : Auto
Write to Read Delay (D) : Auto
Read to Read Delay (S) : Auto
Read to Read Delay (D) : Auto
Write to Write Delay (S) : Auto
Write to Write Delay (D) : Auto

Write to PRE Delay : Auto
Read to PRE Delay : Auto
PRE to PRE Delay : Auto
ALL PRE to ACT Delay : Auto
ALL PRE to REF Delay : Auto

DRAM Static Read Control: Disabled
Dram Read Training : Disabled
MEM OC Charger : Enabled
Ai Clock Twister : Auto
Transaction Booster : Manual

Common Performance Level [10]

Pull-In of CHA PH1 Enabled
Pull-In of CHA PH2 Enabled
Pull-In of CHA PH3 Enabled
Pull-In of CHA PH4 Enabled
Pull-In of CHA PH5 Enabled
Pull-In of CHB PH1 Enabled
Pull-In of CHB PH2 Enabled
Pull-In of CHB PH3 Enabled
Pull-In of CHB PH4 Enabled
Pull-In of CHB PH5 Enabled

PCIE Frequency : 100

CPU Voltage : 1.39
CPU PLL Voltage : 1.56
FSBT : 1.25
DRAM Voltage : 1.9
North Bridge Voltage : 1.25
South Bridge Voltage 1.5 : 1.5
South Bridge Voltage 1.1 : 1.10

CPU GTL Reference 0 : Auto
CPU GTL Reference 1 : -40mv
CPU GTL Reference 2 : Auto
CPU GTL Reference 3 : -40mv
North Bridge GTL Reference : Auto
DDR2 Channel A REF Voltage : Auto
DDR2 Channel B REF Voltage : Auto
North Bridge DDR Reference : Auto

Load Line Calibration : Enabled
CPU Spread Spectrum : Disabled
PCIE Spread Spectrum : Disabled

Looks fine, you did it correctly. You could try all positive values too, it may even help drop your vcore a notch, or it may not be stable, just depends on your cpu. Try:

CPU GTL Reference 0 : +50mv
CPU GTL Reference 1 : +10mv
CPU GTL Reference 2 : +50mv
CPU GTL Reference 3 : +10mv

[psygnosi]

Thanks Cryptik,

I'll try out the values now.

Psygnosi

[CryptiK]

OK anyone struggling on the 266 strap, consider this. I was at:
1112 MHz ram
5-5-5-12-3-30-6-3 @ 2.00v
PL8
266 strap
static read and dram read training disabled
Clock twister on moderate
vNB 1.27

I was pulling ~9500MB/s & 54.5ns in everest



I now have changed this to:

1069MHz ram (1068 real)
5-5-4-12-2-25-4-2 @ 1.94v
PL8
333 strap
static read and dram read training enabled
Clock twister on stronger
vNB 1.27 **EDIT - after testing, this setting needs 1.30 vNB due to aggressive chipset timings, I stopped dual windows memtest at 1500% coverage, which I consider to be stable.

and I get 60mb/s lower read bandwidth, the same write & higher copy bandwidth and 53.9 ns latency.

[Grnfinger]

My new GSkills should be here tomorrow, will allow me to get rid of this mushkin ram and run more aggresive timing @1140MHz
should get very close to 10k r/w/c if not slightly above it

[CryptiK]

I have been doing some testing with Static Read Control & Dram Read Training enabled, and Clock Twister on Strong or Stronger. With Clock Twister set to strong/stronger it takes quite a bit of vNB to stabilize it, I was around 1.37 - 1.45 vNB for the various tests.

The use of SRC & DRT and setting strong or stronger gives a definite boost to bandwidth across the board and reduces latency significantly. At 534 FSB 5:6 Divider I had to drop CT to Strong, as even with 1.49 vNB I could not get into windows. Also notice the latency is almost identical between 500 FSB 5:6 CT Stronger and 534 FSB 5:6 CT Strong.

It appears that Clock Twister lowers latency significantly and has a noticeable but not large effect on bandwidth, and tRD (PL) has a great effect on bandwidth and a moderate effect on latency.

450 FSB 3:4 Divider, PL8, SRC & DRT Enabled, CT Stronger:


450 FSB 3:4 Divider, PL7, SRC & DRT Enabled, CT Stronger:


500 FSB 5:6 Divider, PL8, SRC & DRT Enabled, CT Stronger:


534 FSB 5:6 Divider, PL8, SRC & DRT Enabled, CT Strong:

[Lusken]

Have someone Tried to change the Goop on this motherboard? Someone with Picz?

I want to change this, because my NB and SB temp's are a little hig (I think).

[SiGfever]

My new GSkills should be here tomorrow, will allow me to get rid of this mushkin ram and run more aggresive timing @1140MHz
should get very close to 10k r/w/c if not slightly above it

I too have the same set do in about mid-week.

Edit:

I just changed my settings from "Auto" Dram Read Timing to "Enabled" and Ai Clock Twister from "Moderate" to "Strong" and here are my benches. I did not adjust any timings yet.

[CryptiK]

Have someone Tried to change the Goop on this motherboard? Someone with Picz?

I want to change this, because my NB and SB temp's are a little hig (I think).

Yes I did it and posted pics of the process 2 pages ago.

Here:

http://www.xtremesystems.org/forums/...postcount=1511

[GeorgeVasil]

My new GSkills should be here tomorrow, will allow me to get rid of this mushkin ram and run more aggresive timing @1140MHz
should get very close to 10k r/w/c if not slightly above it
[/IMG]

I too have the same set do in about mid-week.

That's why memoryc run out of stock last week??

Me the third byer..

[CryptiK]

I too have the same set do in about mid-week.

Edit:

I just changed my settings from "Auto" Dram Read Timing to "Enabled" and Ai Clock Twister from "Moderate" to "Strong" and here are my benches. I did not adjust any timings yet.

Do you have Static Read control enabled too? You may have to raise vNB to keep it stable after you make changes to SRC, DRT and Clock twister. Clock twister on strong or stronger uses very aggressive MCH timings
.

[Grnfinger]

1.39vNB should be good up to 475-480FSB

Now if Asus could fix the pull-ins and actually make them work that would be special

[SiGfever]

Do you have Static Read control enabled too? You may have to raise vNB to keep it stable after you make changes to SRC, DRT [B]and Clock twister. Clock twister on strong or stronger uses very aggressive MCH timings
.

Yes it is enabled, here is my complete settings ATM.

Processor:  QX9770
Ai Overclock Tuner: Manual
OC From CPU Level Up: Auto
Ratio CMOS Setting: 9
FSB Frequency: 467
CPU Clock Skew: Normal
NB Clock Skew: Normal
FSB Strap to North Bridge: 333
DRAM Frequency: DDR2-1122MHz

DRAM CLK Skew on Channel A1: Advance 300ps
DRAM CLK Skew on Channel A2: Advance 300ps
DRAM CLK Skew on Channel B1: Advance 300ps
DRAM CLK Skew on Channel B2: Advance 300ps
DRAM Timing Control: Manual

[B]1st Information: [/B]

CAS# Latency: 5 DRAM Clocks
DRAM RAS# to CAS# Delay: 5 DRAM Clocks
DRAM RAS# Precharge: 5 DRAM Clocks
DRAM RAS# Activate to Precharge: 15 DRAM Clocks
RAS# to RAS# Delay:  Auto
Row Refresh Recycle Time: 55 DRAM Clocks
Write Recovery Time: Auto
Read to Precharge Time: Auto

[B]2nd Information:[/B]

Read to Write Delay (S/D): Auto
Write to Read Delay (S): Auto
Write to Read Delay (D): Auto
Read to Read Delay (S): Auto
Read to Read Delay (D): Auto
Write to Write Delay (S): Auto
Write to Write Delay (D): Auto

[B]3rd Information:[/B]

Write to PRE Delay: Auto
Read to PRE Delay: Auto
PRE to PRE Delay: Auto
All PRE to ACT Delay: Auto
All PRE to REF Delay: Auto
DRAM Static Read Control: Enabled
DRAM Read Training: Enabled
MEM. OC Charger: Auto
Ai Clock Twister: Strong
Ai Transaction Booster: Manual

Common Performance Level: 8
Pull-in of CHA PH1: Disabled
Pull-in of CHA PH2: Disabled
Pull-in of CHA PH3: Disabled
Pull-in of CHB PH1: Disabled
Pull-in of CHB PH2: Disabled
Pull-in of CHB PH3: Disabled

PCIE Frequency: 101

CPU Voltage: 1.41250
CPU PLL Voltage: 1.50
FSB Termination Voltage: 1.35175
DRAM Voltage: 2.15775
North Bridge Voltage: 1.39150
South Bridge 1.5 Voltage: 1.50
South Bridge 1.1 Voltage: 1.10

CPU GTL Reference (0): Auto
CPU GTL Reference (1):-40mv
CPU GTL Reference (2): Auto
CPU GTL Reference (3):-40mv
NB GTL Reference: Auto
DDR2 ChA Reference Voltage: Auto
DDR2 ChB Reference Voltage: Auto
North Bridge DDR Reference: Auto

[B]CPU Configuration:[/B]

Ratio CMOS Setting: 9
C1E Support: Disabled
Max CPUID Value Limit: Disabled
Intel Virtualization Tech: Disabled
CPU TM Function: Disabled
Execute Disable Bit: Disabled

Load-Line Calibration: Enabled
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled 

[CryptiK]

1.39vNB should be good up to 475-480FSB

Now if Asus could fix the pull-ins and actually make them work that would be special

Yes, I needed 1.42v for 500 FSB for CT on stronger with SRC & DRT enabled.

And if Asus could make the pullins work it would be awesome. I want the most aggresive chipset timings possible, its the only way to get good clock for clock performance out of the P45. Compared to eva200's gigabyte P45 board the M2F holds its own, I just beat his bandwidth and latency. They should make the timings tighter for each tRD (PL) setting, I don't care if I'd have to run higher vNB to get it stable.

Yes it is enabled, here is my complete settings ATM.

Processor:  QX9770
Ai Overclock Tuner: Manual
OC From CPU Level Up: Auto
Ratio CMOS Setting: 9
FSB Frequency: 467
CPU Clock Skew: Normal
NB Clock Skew: Normal
FSB Strap to North Bridge: 333
DRAM Frequency: DDR2-1122MHz

DRAM CLK Skew on Channel A1: Advance 300ps
DRAM CLK Skew on Channel A2: Advance 300ps
DRAM CLK Skew on Channel B1: Advance 300ps
DRAM CLK Skew on Channel B2: Advance 300ps
DRAM Timing Control: Manual

[B]1st Information: [/B]

CAS# Latency: 5 DRAM Clocks
DRAM RAS# to CAS# Delay: 5 DRAM Clocks
DRAM RAS# Precharge: 5 DRAM Clocks
DRAM RAS# Activate to Precharge: 15 DRAM Clocks
RAS# to RAS# Delay:  Auto
Row Refresh Recycle Time: 55 DRAM Clocks
Write Recovery Time: Auto
Read to Precharge Time: Auto

[B]2nd Information:[/B]

Read to Write Delay (S/D): Auto
Write to Read Delay (S): Auto
Write to Read Delay (D): Auto
Read to Read Delay (S): Auto
Read to Read Delay (D): Auto
Write to Write Delay (S): Auto
Write to Write Delay (D): Auto

[B]3rd Information:[/B]

Write to PRE Delay: Auto
Read to PRE Delay: Auto
PRE to PRE Delay: Auto
All PRE to ACT Delay: Auto
All PRE to REF Delay: Auto
DRAM Static Read Control: Enabled
DRAM Read Training: Enabled
MEM. OC Charger: Auto
Ai Clock Twister: Strong
Ai Transaction Booster: Manual

Common Performance Level: 8
Pull-in of CHA PH1: Disabled
Pull-in of CHA PH2: Disabled
Pull-in of CHA PH3: Disabled
Pull-in of CHB PH1: Disabled
Pull-in of CHB PH2: Disabled
Pull-in of CHB PH3: Disabled

PCIE Frequency: 101

CPU Voltage: 1.41250
CPU PLL Voltage: 1.50
FSB Termination Voltage: 1.35175
DRAM Voltage: 2.15775
North Bridge Voltage: 1.39150
South Bridge 1.5 Voltage: 1.50
South Bridge 1.1 Voltage: 1.10

CPU GTL Reference (0): Auto
CPU GTL Reference (1):-40mv
CPU GTL Reference (2): Auto
CPU GTL Reference (3):-40mv
NB GTL Reference: Auto
DDR2 ChA Reference Voltage: Auto
DDR2 ChB Reference Voltage: Auto
North Bridge DDR Reference: Auto

[B]CPU Configuration:[/B]

Ratio CMOS Setting: 9
C1E Support: Disabled
Max CPUID Value Limit: Disabled
Intel Virtualization Tech: Disabled
CPU TM Function: Disabled
Execute Disable Bit: Disabled

Load-Line Calibration: Enabled
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled 

Not bad at all, can you run CT = Stronger? Should drop the latency a bit more and give you a little more bandwidth.