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Thread: ASUS Maximus II Formula - new P45 king?

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  1. #11
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    Quote Originally Posted by Codeman05 View Post
    Guys...need some help.

    Recently replaced my dying 780i with this Maxumus II Formula, but I'm running into some problems.
    This cpu did 4.5GHz with ease on the 780, however right now I'm struggling with 4.1 GHz.

    The problem seems to be that the only way I can get past 400FSB is with the 400MHz Strap and the 4:3 divisor.
    The only problem with that is I am then limited to ~430 FSB (DDR 1146).

    I would like to use the 1:1 divisor and drop my multi, but if the FSB is at all over 400, with the 1:1 divisor the MB will not post.
    The LCD freezes at "DET DRAM".

    Any suggestions?

    Here is my working config...changing the divisor to 1:1 again results in no post.
    Code:
    Ai Overclock Tuner: Manual
    OC From CPU Level Up: Auto
    Ratio CMOS Setting: 9.5
    FSB Frequency: 430
    CPU Clock Skew: Normal
    NB Clock Skew: Normal
    FSB Strap to North Bridge: 400
    DRAM Frequency: DDR2-1146Mhz
    DRAM CLK Skew on Channel A1: Auto
    DRAM CLK Skew on Channel A2: Auto
    DRAM CLK Skew on Channel B1: Auto
    DRAM CLK Skew on Channel B2: Auto
    DRAM Timing Control: Manual
    
    1st Information:
    
    CAS# Latency: 5 DRAM Clocks
    DRAM RAS# to CAS# Delay: 5 DRAM Clocks
    DRAM RAS# Precharge: 5 DRAM Clocks
    DRAM RAS# Activate to Precharge: 18 DRAM Clocks
    RAS# to RAS# Delay: 5
    Row Refresh Recycle Time: 60 
    Write Recovery Time: 6
    Read to Precharge Time: 5
    
    2nd Information:
    
    Read to Write Delay (S/D): 10
    Write to Read Delay (S): 4
    Write to Read Delay (D): 5
    Read to Read Delay (S): 6
    Read to Read Delay (D): 6
    Write to Write Delay (S): 5
    Write to Write Delay (D): 6
    
    3rd Information:
    
    Write to PRE Delay: 16
    Read to PRE Delay: 6
    PRE to PRE Delay: 1
    All PRE to ACT Delay: 6
    All PRE to REF Delay: 6
    DRAM Static Read Control: Disabled
    DRAM Read Training: Disabled
    MEM. OC Charger: Enabled
    Ai Clock Twister: Moderate
    Ai Transaction Booster: Manual
    
    Common Performance Level: 8
    Pull-in of CHA PH1: Disabled
    Pull-in of CHA PH2: Disabled
    Pull-in of CHA PH3: Disabled
    Pull-in of CHB PH1: Disabled
    Pull-in of CHB PH2: Disabled
    Pull-in of CHB PH3: Disabled
    
    PCIE Frequency: 100
    
    CPU Voltage: tried 1.40
    CPU PLL Voltage: 1.50
    FSB Termination Voltage: 1.4
    DRAM Voltage: 2.2
    North Bridge Voltage: 1.35
    South Bridge 1.5 Voltage: 1.50
    South Bridge 1.1 Voltage: 1.10
    
    CPU GTL Reference (0): +20
    CPU GTL Reference (1): +20
    CPU GTL Reference (2): +20
    CPU GTL Reference (3): +20
    NB GTL Reference: Auto
    DDR2 ChA Reference Voltage: Auto
    DDR2 ChB Reference Voltage: Auto
    North Bridge DDR Reference: Auto
    
    CPU Configuration:
    
    Ratio CMOS Setting: 9.5
    C1E Support: Disabled
    Max CPUID Value Limit: Disabled
    Intel Virtualization Tech: Disabled
    Execute Disable Bit: Disabled
    
    Load-Line Calibration: Disabled
    CPU Spread Spectrum: Disabled
    PCIE Spread Spectrum: Disabled
    Thanks for the help
    Up PL to 10 for now. 10 is lowest you can go 1:1. Maybe some more vNB will help. Also set DRAM CLK Skew to advance 250
    Last edited by nugzo; 10-24-2008 at 09:39 PM.
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