ASUS Maximus II Formula - new P45 king?

[SiGfever]

Do you have Static Read control enabled too? You may have to raise vNB to keep it stable after you make changes to SRC, DRT [B]and Clock twister. Clock twister on strong or stronger uses very aggressive MCH timings
.

Yes it is enabled, here is my complete settings ATM.

Processor:  QX9770
Ai Overclock Tuner: Manual
OC From CPU Level Up: Auto
Ratio CMOS Setting: 9
FSB Frequency: 467
CPU Clock Skew: Normal
NB Clock Skew: Normal
FSB Strap to North Bridge: 333
DRAM Frequency: DDR2-1122MHz

DRAM CLK Skew on Channel A1: Advance 300ps
DRAM CLK Skew on Channel A2: Advance 300ps
DRAM CLK Skew on Channel B1: Advance 300ps
DRAM CLK Skew on Channel B2: Advance 300ps
DRAM Timing Control: Manual

[B]1st Information: [/B]

CAS# Latency: 5 DRAM Clocks
DRAM RAS# to CAS# Delay: 5 DRAM Clocks
DRAM RAS# Precharge: 5 DRAM Clocks
DRAM RAS# Activate to Precharge: 15 DRAM Clocks
RAS# to RAS# Delay:  Auto
Row Refresh Recycle Time: 55 DRAM Clocks
Write Recovery Time: Auto
Read to Precharge Time: Auto

[B]2nd Information:[/B]

Read to Write Delay (S/D): Auto
Write to Read Delay (S): Auto
Write to Read Delay (D): Auto
Read to Read Delay (S): Auto
Read to Read Delay (D): Auto
Write to Write Delay (S): Auto
Write to Write Delay (D): Auto

[B]3rd Information:[/B]

Write to PRE Delay: Auto
Read to PRE Delay: Auto
PRE to PRE Delay: Auto
All PRE to ACT Delay: Auto
All PRE to REF Delay: Auto
DRAM Static Read Control: Enabled
DRAM Read Training: Enabled
MEM. OC Charger: Auto
Ai Clock Twister: Strong
Ai Transaction Booster: Manual

Common Performance Level: 8
Pull-in of CHA PH1: Disabled
Pull-in of CHA PH2: Disabled
Pull-in of CHA PH3: Disabled
Pull-in of CHB PH1: Disabled
Pull-in of CHB PH2: Disabled
Pull-in of CHB PH3: Disabled

PCIE Frequency: 101

CPU Voltage: 1.41250
CPU PLL Voltage: 1.50
FSB Termination Voltage: 1.35175
DRAM Voltage: 2.15775
North Bridge Voltage: 1.39150
South Bridge 1.5 Voltage: 1.50
South Bridge 1.1 Voltage: 1.10

CPU GTL Reference (0): Auto
CPU GTL Reference (1):-40mv
CPU GTL Reference (2): Auto
CPU GTL Reference (3):-40mv
NB GTL Reference: Auto
DDR2 ChA Reference Voltage: Auto
DDR2 ChB Reference Voltage: Auto
North Bridge DDR Reference: Auto

[B]CPU Configuration:[/B]

Ratio CMOS Setting: 9
C1E Support: Disabled
Max CPUID Value Limit: Disabled
Intel Virtualization Tech: Disabled
CPU TM Function: Disabled
Execute Disable Bit: Disabled

Load-Line Calibration: Enabled
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled