X48 Rampage Formula Preview.

[Zucker2k]

argh you got yourself confused!

dimm1 - 4 clock fine delay are mch internal timings, associated with the clock strobe for the handshake between mch and dram for read delay (tRD). if you pull in any phase but the last one under AI transaction booster or similar, those values change..and if u pull in the last phase the read delay phase adjust value changes.

Mikeyakame, I know what I'm talking about; what you term as handshake, is what I've explained as "latency" denoted by the "t" appendage in everest. DRAM clock skews do impact the read delay phase adjust, and I've experimented with it enough to know this. Below is an example:

I switched to Advance 300 on both A/B channels and now see how both diims on have the same latency? Now go back to my previous and check the 300/350 advance setting and you'll realise dimm A1 is slower than A2 by 1t. So where exactly am I confused?