Quote Originally Posted by Zucker2k View Post
Let me help; the DRAM Skews help optimize latency between individual dimms (since they're positioned at different distances from the NB) and the NB. The following screenshots show:

Q9550 @ 8.5x475
G.Skills PC2-8500 @ 1140, 2.128v
VNB @ 1.550v
DRAM Static Read Control = Enabled
AiClock Twister = Stronger
DRAM Skews A = 250
B = 350
argh you got yourself confused!

dimm1 - 4 clock fine delay are mch internal timings, associated with the clock strobe for the handshake between mch and dram for read delay (tRD). if you pull in any phase but the last one under AI transaction booster or similar, those values change..and if u pull in the last phase the read delay phase adjust value changes.