X48 Rampage Formula Preview.

[Zucker2k]

Let me help; the DRAM Skews help optimize latency between individual dimms (since they're positioned at different distances from the NB) and the NB. The following screenshots show:

Q9550 @ 8.5x475
G.Skills PC2-8500 @ 1140, 2.128v
VNB @ 1.550v
DRAM Static Read Control = Enabled
AiClock Twister = Stronger
DRAM Skews A = 250
B = 350

[chris8325]

thanks a lot for your help Zucker2k
but still not sure if i got it -
all i have to do is tweak my skew settings
to get the lowest values for "clock fine delay" in everest ?
that´s it ?
always thought i have to push the chipset and ram to its
limits (of course without changing fsb) and than test with
different skew settings ...

[Zucker2k]

thanks a lot for your help Zucker2k
but still not sure if i got it -
all i have to do is tweak my skew settings
to get the lowest values for "clock fine delay" in everest ?
that´s it ?
always thought i have to push the chipset and ram to its
limits (of course without changing fsb) and than test with
different skew settings ...

The skews are not about getting the lowest latency, they're about dictating length of signals. When I'm running 500FSB 1:1, for example, my channel A latency is usually around 12t. If I had all four ram slots populated for this particular overclock, the latencies would have shown different because the NB would be working harder.

You can further adjust skews to lengthen signal even further by delaying skews; keep in mind that for this shot, I advanced channel B to the maximum possible, usually, that dictates or sets the lowest margin for operation. This is all aimed at playing nice with your overclock. Generally, this is not necessary, but if you want to wring everything out of your ram (in my case, my ram 2x2Gb G.Skill is holding me back) then these fine-tuning or adjustments are handy in accomplishing that.

[mikeyakame]

Let me help; the DRAM Skews help optimize latency between individual dimms (since they're positioned at different distances from the NB) and the NB. The following screenshots show:

Q9550 @ 8.5x475
G.Skills PC2-8500 @ 1140, 2.128v
VNB @ 1.550v
DRAM Static Read Control = Enabled
AiClock Twister = Stronger
DRAM Skews A = 250
B = 350

argh you got yourself confused!

dimm1 - 4 clock fine delay are mch internal timings, associated with the clock strobe for the handshake between mch and dram for read delay (tRD). if you pull in any phase but the last one under AI transaction booster or similar, those values change..and if u pull in the last phase the read delay phase adjust value changes.

[Zucker2k]

argh you got yourself confused!

dimm1 - 4 clock fine delay are mch internal timings, associated with the clock strobe for the handshake between mch and dram for read delay (tRD). if you pull in any phase but the last one under AI transaction booster or similar, those values change..and if u pull in the last phase the read delay phase adjust value changes.

Mikeyakame, I know what I'm talking about; what you term as handshake, is what I've explained as "latency" denoted by the "t" appendage in everest. DRAM clock skews do impact the read delay phase adjust, and I've experimented with it enough to know this. Below is an example:

I switched to Advance 300 on both A/B channels and now see how both diims on have the same latency? Now go back to my previous and check the 300/350 advance setting and you'll realise dimm A1 is slower than A2 by 1t. So where exactly am I confused?

[mikeyakame]

Mikeyakame, I know what I'm talking about; what you term as handshake, is what I've explained as "latency" denoted by the "t" appendage in everest. DRAM clock skews do impact the read delay phase adjust, and I've experimented with it enough to know this. Below is an example:

I switched to Advance 300 on both A/B channels and now see how both diims on have the same latency? Now go back to my previous and check the 300/350 advance setting and you'll realise dimm A1 is slower than A2 by 1t. So where exactly am I confused?

What I meant was confused in explanation not understanding. I realised you know what you are talking about so I don't question your knowledge, rather just the outline topic of what you summarized. I'd be curious to see if the CMD skews have any effect on those values, I can't run 1N command rate to see what effect they have if any on those particular handshake timings. I do know that by changing the skew of the clock strobe on any slot does change the value of DIMMx Fine Clock Delay on the DRAM controller side, but also when you pull in certain tRD clock strobe phases on the MCH side it has a counterproductive effect on those handshake / latency timings.