Quote Originally Posted by Grnfinger View Post
Something you might want to try is a positive value for GTL's.
I ran the correct values for my setup -50 or something like that and coudnt get 2 cores stable.
Adjusting to a positive value
ie +30 +20 +20 +30 got my chip stable fast and allowed me to lower PLL to its min, and vcore was also lowerd 2 notches.
Not saying its going to work but its worth a shot?
I tried some settings from one of your posted OC's. It failed core 1 after 52min runtime. Here are the settings.

PHP Code:
Ai Overclock TunerManual
OC From CPU Level Up
Auto
Ratio CMOS Setting
8.5
FSB Frequency
436
CPU Clock Skew
Normal
NB Clock Skew
Normal
FSB Strap to North Bridge
333
DRAM Frequency
DDR2-1047MHz

DRAM CLK Skew on Channel A1
Advance 300ps
DRAM CLK Skew on Channel A2
Advance 300ps
DRAM CLK Skew on Channel B1
Advance 300ps
DRAM CLK Skew on Channel B2
Advance 300ps
DRAM Timing Control
Manual

1st Information


CAS# Latency: 5 DRAM Clocks
DRAM RAS# to CAS# Delay: 5 DRAM Clocks
DRAM RAS# Precharge: 5 DRAM Clocks
DRAM RAS# Activate to Precharge: 15 DRAM Clocks
RAS# to RAS# Delay:  Auto
Row Refresh Recycle Time55 DRAM Clocks
Write Recovery Time
Auto
Read to Precharge Time
Auto

2nd Information
:

Read to Write Delay (S/D): Auto
Write to Read Delay 
(S): Auto
Write to Read Delay 
(D): Auto
Read to Read Delay 
(S): Auto
Read to Read Delay 
(D): Auto
Write to Write Delay 
(S): Auto
Write to Write Delay 
(D): Auto







3rd Information
:

Write to PRE DelayAuto
Read to PRE Delay
Auto
PRE to PRE Delay
Auto
All PRE to ACT Delay
Auto
All PRE to REF Delay
Auto
DRAM 
Static Read ControlEnabled
DRAM Read Training
Auto
MEM
OC ChargerAuto
Ai Clock Twister
Stronger
Ai Transaction Booster
Manual

Common Performance Level
10
Pull
-in of CHA PH1Disabled
Pull
-in of CHA PH2Disabled
Pull
-in of CHA PH3Disabled
Pull
-in of CHB PH1Disabled
Pull
-in of CHB PH2Disabled
Pull
-in of CHB PH3Disabled

PCIE Frequency
101

CPU Voltage
1.4250
CPU PLL Voltage
1.50
FSB Termination Voltage
1.33850
DRAM Voltage
2.12
North Bridge Voltage
1.39150
South Bridge 1.5 Voltage
1.50
South Bridge 1.1 Voltage
1.10

CPU GTL Reference 
(0): +20mv
CPU GTL Reference 
(1): +10mv
CPU GTL Reference 
(2): +10mv
CPU GTL Reference 
(3): +20mv
NB GTL Reference
Auto
DDR2 ChA Reference Voltage
Auto
DDR2 ChB Reference Voltage
Auto
North Bridge DDR Reference
Auto









CPU Configuration
:

Ratio CMOS Setting8.5
C1E Support
Disabled
Max CPUID Value Limit
Disabled
Intel Virtualization Tech
Disabled
CPU TM 
Function: Disabled
Execute Disable Bit
Disabled

Load
-Line CalibrationEnabled
CPU Spread Spectrum
Disabled
PCIE Spread Spectrum
Disabled