Quote Originally Posted by mikeyakame View Post

DRAM Read ODT 3T
DRAM Write ODT 6T
MCH Read ODT 8T
Performance Level 7
Read Delay Phase Adjust +5T
DIMM1 Clock Fine Delay 13T
DIMM2 Clock Fine Delay 11T
DIMM3 Clock Fine Delay 10T
DIMM4 Clock Fine Delay 8T
How do you understand from above data that you have correctly setup the enabled/disabled phase data for your configuration?

Actually I am at FSB 450, strap 333, divider 5/6, performance level 8 and every phase on ENABLED. I have DRAM skew put to ADVANCED 250 ps both channels as if I follow your suggestion to put A 50 ps delay and B 300 ps advance, I have big instability.

Following your test and guess, I may change to DISABLED some phases....can I understand which one from above Everest values?