X48 Rampage Formula Preview.

[Eurasianman]

If you are crashing at idle with LLC enabled, your board is defective, and there is no getting around that. It is not a BIOS problem, it is a hardware problem. My original Rampage Formula that had the issue had the same BIOS as my new one that does not have the issue (0403).

What if you've replaced the TIM on the NB and SB?

Not that I'm having any issues or anything with my motherboard. Just wondering.

[003]

Replacing the TIM is fine, I replaced it on mine and they didn't have a problem. I did kind of neglect to mention it, but still

[bigslappy]

Noo, my board .. since i can't live without my precious

YEAH !!
That's HOW ... I got 2 R/FX48's now !! couldn't live with out it !!
............. .........................

SOO i bought another
....... ;p

I think I need MoBo ReHaB !

[DaLiu]

One question about VTT, according to INTEL no more than 1,4 V on VTT, i set on my Rampage Formula 1,38 V in BIOS and according to hardware monitor from BIOS and other software the real voltage is 1,28 V. What is the real value?

[SoLoR]

using 1.46 in bios that gives 1.38V real, so i assume 1 step more (1.48) gives 1.4, altho in all honesty "auto" settings with high FSB are 1.41V real...

[Chruschef]

so I just ordered one of these boards from new egg,
I'm running
1000w PSU,
2gigs of mushkin RAM at 1066mhz(http://www.newegg.com/Product/Produc...82E16820146789)
and a QX6700

Anyone wanna throw me some basic settings to start my overclocking with?'
I'm a bit of a noob OC'er...

[Malik]

Which bios is the best for this mobo ?

I have 0308 and i thinking about 0408 - any opinion ?

[panheimer]

Can someone teach me about these settings?
I know it's related to Common Performance Level, and have read somewhere that when you can't get to a lower PL, you may try enable these settings to get better performance.
Well, i've setted to 450x8, fsb strap 266 and ram @1125, with a PL7. Wather i put in, settings a PL6 hangs the system on "det dram".
So i've started playing with PL7 and these Pull-IN of CHA...and got something out of it with these settings:
Pull-In of CHA PH1: Enabled
Pull-In of CHA PH2: Disabled
Pull-In of CHA PH3: Enabled
Pull-In of CHA PH4: Enabled
Pull-In of CHB PH1: Enabled
Pull-In of CHB PH2: Disabled
Pull-In of CHB PH3: Disabled
Pull-In of CHB PH4: Enabled
So i was able to enable five of these pull in, with a gain in everest of about 100 MB/s in read and 2.0 ns in latency, while other results remain more or less the same.
If i try to enable CHA PH2, CHB PH2 and CHB PH3 the system hangs on det dram again. Well, i supposed tha if i can enable CHA PH3 i would be able to enable also CHB PH3, but it's not true...why?

[mikeyakame]

You need to understand their relationship to make use of them. Number of phases is equal to divider in use. Ie 5:6 has 5 phases, 3:4 has 3 phases, etc. Its DRAM phase : FSB phase. If you cant achieve lower PL then you can use the Phase Pull-in to tighten tRD for particular Phases. The way it works is if you are running 3:4 and PL7 for example. It would look like this for pull in.

A1 A2 A3 B1 B2 B3
06 07 06 06 07 06

Pull-in CHA PH1 = Enabled
Pull-in CHA PH2 = Disabled
Pull-in CHA PH3 = Enabled
Pull-in CHB PH1 = Enabled
Pull-in CHB PH2 = Disabled
Pull-in CHB PH3 = Enabled

The reason is you can only pull in phases where there is alignment between FSB and DRAM. In this case 3:4

___ ___ ___
_/A1 \___/A2 \___/A3 \_ <== tRD Phases from DRAM to MCH (Data Out)
__ __ __ __
_/1 \__/2 \__/3 \__/4 \_ <== tCK DRAM operational Clock Phases (Data Request)

3 Data Out clocks for every 4 DRAM operation Clocks

Thats a poor diagram but should give u an idea

See how there is Alignment with A1 to 1, A3 to 4, this is why you can only pull in those two phases. Pulling in A2 would create a situation where you cannot align clock phases for tRD at MCH or DRAM and you get data corruption or window too small to complete read op.

[Clump]

Here's my 24/7 overclock. It's 2 hours OCCT stable and 8 hours + prime stable.

Running the 0406 beta BIOS.

Settings:

AI Overclock Tuner.............................. Manual
CPU Ratio Setting............................... 10.0
FSB Strap to North Bridge....................... 333MHz
FSB Frequency................................... 400MHz
PCI-E Frequency................................. 101MHz

DRAM Frequency.................................. DDR2 – 961MHz
DRAM Command Rate............................... 2N
DRAM CMD Skew on Channel A...................... Auto
DRAM CMD Skew on Channel B...................... Auto
DRAM CLK Skew on Channel A...................... Auto
DRAM CLK Skew on Channel B...................... Auto
DRAM Timing Control............................. Auto
DRAM Static Read Control........................ Ensabled
AI Clock Twister................................ Strong
AI Transaction Twister.......................... Manual

Common Performance Level.................... 07
Pull-In of CHA PH1.......................... Disabled
Pull-In of CHA PH2.......................... Disabled
Pull-In of CHA PH3.......................... Disabled
Pull-In of CHA PH4.......................... Disabled
Pull-In of CHB PH1.......................... Disabled
Pull-In of CHB PH2.......................... Disabled
Pull-In of CHB PH3.......................... Disabled
Pull-In of CHB PH4.......................... Disabled

CPU Voltage..................................... 1.48125V
CPU PLL Voltage................................. 1.54V
Northbridge Voltage............................. 1.35V
DRAM Voltage.................................... 2.10V
FSB Termination Voltage......................... 1.32V
South Bridge Voltage............................ Auto
SB 1.50V Voltage................................ Auto
Loadline Calibration............................ Disabled
CPU GTL Voltage REF............................. 0.63x
NB GTL Voltage REF.............................. 0.67x
DRAM Controller Voltage REF..................... Auto
DRAM Channel A Voltage REF...................... DDR_REF + 10mV
DRAM Channel B Voltage REF...................... DDR_REF + 10mV

CPU Spread Spectrum............................. Disabled
PCI-E Spread Spectrum........................... Disabled

My memory would not run at 1066. Prime would error out on blend. I'd like to get it to 1000, but the 266 strap won't boot. There's some more tweaking to do on the memory side.

My north bridge is HOT. I have the included ASUS fan on the regulators and 2 40mm fans directly on the north bridge. After an hour of OCCT it's 66C! It idles in the low 50s. Lower voltages lead to instability, so that's it for now. Once I get the ambition to tear everything apart I'll put a water block, or aftermarket cooler on it. My hottest core was 57C after the 8 hour prime95 run.

[mikeyakame]

Can someone teach me about these settings?
I know it's related to Common Performance Level, and have read somewhere that when you can't get to a lower PL, you may try enable these settings to get better performance.
Well, i've setted to 450x8, fsb strap 266 and ram @1125, with a PL7. Wather i put in, settings a PL6 hangs the system on "det dram".
So i've started playing with PL7 and these Pull-IN of CHA...and got something out of it with these settings:
Pull-In of CHA PH1: Enabled
Pull-In of CHA PH2: Disabled
Pull-In of CHA PH3: Enabled
Pull-In of CHA PH4: Enabled
Pull-In of CHB PH1: Enabled
Pull-In of CHB PH2: Disabled
Pull-In of CHB PH3: Disabled
Pull-In of CHB PH4: Enabled
So i was able to enable five of these pull in, with a gain in everest of about 100 MB/s in read and 2.0 ns in latency, while other results remain more or less the same.
If i try to enable CHA PH2, CHB PH2 and CHB PH3 the system hangs on det dram again. Well, i supposed tha if i can enable CHA PH3 i would be able to enable also CHB PH3, but it's not true...why?

The reason you cant pull in CHB PH3 is because there isn't enough skewing to correct CHB clock phases. You can try adjust CHB CLK skews with a little advance and see if it helps. Be warned if you set tRD phase skewing too tight you will corrupt your CMOS instantaneously, be sure to use OC Profiles to save your settings before you try too tight phase skewing. Try changing your strap also, 266 strap is a bit meh. I use 333 or 400 I find they are better at higher FSBs.

There is also a rule that applies that you must pull in PH1 of either before you are allowed to pull in any other phases or you cause misalignment.

[GAR]

I just replaced by NB with Thermaltake spirit II and idles now at 46-48 and loads 50-55

[panheimer]

... Be warned if you set tRD phase skewing too tight you will corrupt your CMOS instantaneously,....

???it's a bit scaring! What do you mean? That i would have to simply clear cmos or that i corrupts bios and have to reflash it?

And what each phase is intended to do? In wich way they affects performance?
I've found that PH1 improves read bandwidth and PH3 improves latency while PH4 seems to do nothing. Is it true or was only my impression?

[mikeyakame]

It should automatically clear cmos for you if it corrupts. Just the cmos data, no reflashing of course. I've corrupted it many times, I use OC profile to save my settings first just incase so I can reload them.


It could be that every phase but the last 1 or 2 depending on divider alter Memory Clock Phase delays to line up Memory & Data clocks, and the last 1 or 2 phases are tRD phases (Data/Memory phase). Thats my best guess. There isn't much information about how this exactly works. I understand it with close dividers, but as you use larger ones I am not sure what refers to what.

For 1:1 there are 2 phases. Clock & data. 3:4 has 3 phases. 2 Clock and 1 data. 5:6 has 5 Phases, 3 clock & 2 data? or 4 clock and 1 data and so on. Everest can show you which you are altering exactly by looking at Read Delay Phase Adjust and Dimm 1 - 4 Clock Fine Delay values and how they change as you pull phases in and out.

DRAM Read ODT 3T
DRAM Write ODT 6T
MCH Read ODT 8T
Performance Level 7
Read Delay Phase Adjust +5T
DIMM1 Clock Fine Delay 13T
DIMM2 Clock Fine Delay 11T
DIMM3 Clock Fine Delay 10T
DIMM4 Clock Fine Delay 8T

Thats my everest timing printout with PL 7, A1 A3 B1 B3 Pulled in to PL6. A2 and B2 are left at PL7. Thats with 3:4 divider, 333 strap ( i think). Phase A3/B3 alter Read Delay Phase Adjust value.

[mikeyakame]

heres a cmos dump of mine if you want to have a look at it. 8x430FSB DDR2-1146 Q6600. Unzip it and put it on a USB flash drive and load it through Start OC Profile. Make sure to save your OC profile first, either to 1 or 2 or flash drive. Be careful with the DRAM voltage, as I've got it running at 2.32V real ( +20mV dram ref voltage (0.02V) ) . All the other voltages are sane and won't cause you any grief. It's also setup for RAID and wireless keyboard just so you know. Loading it will load all the CMOS settings. Not just the OC ones.

[mikeyakame]

I just replaced by NB with Thermaltake spirit II and idles now at 46-48 and loads 50-55

Is that good or bad? Worse or better than before.

[Brama]

DRAM Read ODT 3T
DRAM Write ODT 6T
MCH Read ODT 8T
Performance Level 7
Read Delay Phase Adjust +5T
DIMM1 Clock Fine Delay 13T
DIMM2 Clock Fine Delay 11T
DIMM3 Clock Fine Delay 10T
DIMM4 Clock Fine Delay 8T

How do you understand from above data that you have correctly setup the enabled/disabled phase data for your configuration?

Actually I am at FSB 450, strap 333, divider 5/6, performance level 8 and every phase on ENABLED. I have DRAM skew put to ADVANCED 250 ps both channels as if I follow your suggestion to put A 50 ps delay and B 300 ps advance, I have big instability.

Following your test and guess, I may change to DISABLED some phases....can I understand which one from above Everest values?

[panheimer]

WOW! Thanks very much mikeyakame! I've read all of your post and learned many things - the most still remain a little too hard for me to completely acquire, but now i'm starting to understand the way settings works.
I'll try your profile, to learn something more from your work.
thanks again

p.s.: have you ever think do post a fully comprehensive guide about this mobo and its settings?

[mikeyakame]

How do you understand from above data that you have correctly setup the enabled/disabled phase data for your configuration?

Actually I am at FSB 450, strap 333, divider 5/6, performance level 8 and every phase on ENABLED. I have DRAM skew put to ADVANCED 250 ps both channels as if I follow your suggestion to put A 50 ps delay and B 300 ps advance, I have big instability.

Following your test and guess, I may change to DISABLED some phases....can I understand which one from above Everest values?

With skews easiest way to see which settings work and which don't is by using Test #5 in memtest86+ find settings which give you minor errors and adjust skews to see whether the errors occur earlier or later. Just try leaving Channel B on normal, and delaying Channel A bit by bit and see if its any more or less stable. Takes time, skews only really help at much higher DRAM frequency. I don't really need to skew CHB much until I push past 1160mhz. I run CHA with delay of 250PS atm, and CHB on auto at 1150 5-5-5-15 and 2.3v.

Also from everest, you can tell I've pulled in the last 1 or 2 phases from Read Delay Phase Adjust. The Dimm Fine clock adjust means i've pulled in or pulled out The first 2-3 phases (depending on divider). For 5:6 divider I would try Pull in A1 / A4 / A5 /B1 / B4 / B5. A1 / B1 first, then others. A4 / B4 / A5 / B5 should alter Read delay phase adjust. Others should alter Dimm Clock Fine Adjust. Im 90% PH4 alters it, but I know PH5 definitely does.

In everest cache benchmark i get ~ 52.8ns / 0.9ns / 3.5ns. This ram struggles to push much lower latency than that. Lowest I've gotten was around 51.2ns / 0.7ns / 3.4ns at 490fsb

Note that skews aren't constant values, they change as DRAM frequency changes. Trace lengths are relative to the clocking frequency.

[GAR]

Is that good or bad? Worse or better than before.

Much better, now idles at 41c and loads at 48-50c, great cooler for 20 bucks, my stock wasnt even making contact with the NB fully.

here is a pic

[Chruschef]

So, i just tried to build my own computer for the first time with an X48 asus rampage.. I thought I would just be able to hook everything up with power and then get going from there..
Previously I have just built on to other computers that I purchased(an alienware)
so i bought a 1000w Zalman, GTX280, 2gigs mushkin RAM, and an X48 Asus Rampage Forumla, but the only thing I get when i press the on button is CPU INIT on the external LCD poster... What does it mean, what do I do?

Entire computer specs are as follow
COSMOS S case(new)
QX6700(carried over from last computer)
2x 500 gig Seagate (carried from last computer)
X48 Asus Rampage Formula (new)
GTX280(carried from last computer, but still new kind of)
Blu-Ray CD drive (carried over from last computer)
2x 2 gig Mushkin RAM(new)

One thing that I've noticed is that when I plug only one of the 4 pin connectors into the CPU power slot everything boots, but still CPU Init.
When I plug in both of them, nothing boots just tries to turn on and then immediatley crashes.

[Vivi]

Put of the power supply. Wait for all the lights to go off (wait for the power to drain from resistors).

Then put power supply back on. and press the CLR CMOS button and keep it pressed for 10 seconds. then release and press the power on button again.

Goodluck

[Chruschef]

tried that.. Now it won't turn on at all.. just a flash of lights then off.'
and to elaborate on my problem, nothing comes on the screen at all. Doesn't even begin to show something.

[panheimer]

The reason you cant pull in CHB PH3 is because there isn't enough skewing to correct CHB clock phases. You can try adjust CHB CLK skews with a little advance and see if it helps. Be warned if you set tRD phase skewing too tight you will corrupt your CMOS instantaneously, be sure to use OC Profiles to save your settings before you try too tight phase skewing. Try changing your strap also, 266 strap is a bit meh. I use 333 or 400 I find they are better at higher FSBs.

There is also a rule that applies that you must pull in PH1 of either before you are allowed to pull in any other phases or you cause misalignment.

As you suggested i've tried correcting CHB skew, but even with 50 advance i immediately got the cmos corrupted...tried higher advance but worthless always corrupt cmos. si i've tried to delay CHB skew, no more cmos corruption but still hang on det dram and no post.
in the end, with my current settings i'm not able to enable CHB PH3, and while priming with CHA PH3 enabled i've got a bsod...so i've disabled also CHA PH3.
BTW now i can confirm that with a 4:5 multiplier on ram, the PH3 affects memory latency: with CHA PH3 enabled i've reached 50.4 ns, while now with it disabled i've returned to 52.2 while cache L1 and L2 remained at 0.8 and 3.2 in with both cases.

[mikeyakame]

As you suggested i've tried correcting CHB skew, but even with 50 advance i immediately got the cmos corrupted...tried higher advance but worthless always corrupt cmos. si i've tried to delay CHB skew, no more cmos corruption but still hang on det dram and no post.
in the end, with my current settings i'm not able to enable CHB PH3, and while priming with CHA PH3 enabled i've got a bsod...so i've disabled also CHA PH3.
BTW now i can confirm that with a 4:5 multiplier on ram, the PH3 affects memory latency: with CHA PH3 enabled i've reached 50.4 ns, while now with it disabled i've returned to 52.2 while cache L1 and L2 remained at 0.8 and 3.2 in with both cases.

nice work! all you can do I suppose is give it more vNB, that's the only way to tighten up PL any farther.