It should automatically clear cmos for you if it corrupts. Just the cmos data, no reflashing of course. I've corrupted it many times, I use OC profile to save my settings first just incase so I can reload them.
It could be that every phase but the last 1 or 2 depending on divider alter Memory Clock Phase delays to line up Memory & Data clocks, and the last 1 or 2 phases are tRD phases (Data/Memory phase). Thats my best guess. There isn't much information about how this exactly works. I understand it with close dividers, but as you use larger ones I am not sure what refers to what.
For 1:1 there are 2 phases. Clock & data. 3:4 has 3 phases. 2 Clock and 1 data. 5:6 has 5 Phases, 3 clock & 2 data? or 4 clock and 1 data and so on. Everest can show you which you are altering exactly by looking at Read Delay Phase Adjust and Dimm 1 - 4 Clock Fine Delay values and how they change as you pull phases in and out.
DRAM Read ODT 3T
DRAM Write ODT 6T
MCH Read ODT 8T
Performance Level 7
Read Delay Phase Adjust +5T
DIMM1 Clock Fine Delay 13T
DIMM2 Clock Fine Delay 11T
DIMM3 Clock Fine Delay 10T
DIMM4 Clock Fine Delay 8T
Thats my everest timing printout with PL 7, A1 A3 B1 B3 Pulled in to PL6. A2 and B2 are left at PL7. Thats with 3:4 divider, 333 strap ( i think). Phase A3/B3 alter Read Delay Phase Adjust value.
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