Quote Originally Posted by KTE View Post
From looking at Dr. Hasans research and papers (one of the chief scientists heading IBM/AMD 45nm technology) it looks to be a 32nm implementation and not until then, they don't have the mass tooling required either. They've gone past the first phase of research, process, initial product test but not far past that that I know of. It's certainly a future target..
Yeah, when you posted that information it got me thinking... when D. Wang published his summary information from the 2007 IEDM (http://www.realworldtech.com/page.cf...1608222300&p=6) I missed the info about him taking the ITSA NMOS numbers from the VLSI Symposium in June. The 2007 IEDM proceedings have been published, but I could not find anything on current state of ITSA 45 nm, thinking I just simply passed over it I took the RTW data at face value.

So, prodding a little, I noted the footnote, looked up the VLSI paper and wolla .. D. Wang is quoting intial HK/MG data from the IBM paper I linked above -- to date we only know that AMD will not initially use HK/MG so that data is irrelevant in that regard. Weird also in that data was generated before last Jan. so using his information is terribly in error ... we don't know diddly squat, that data is simply too old, too much can change and is different.

Nonetheless, the (110) technology is extraordinarily interesting, especially in the SOI implementation -- as I understand from reading up on this, one must 'dig' a hole and selective grow (110) oriented Si to form the device. From the experimental data, they can push to near 1 mA/um which is just a hair shy of a MG NMOS device... this is impressive. If they do cut it in at 32 nm, together the HK/MG this will be something very special indeed.

Jack