Phenom 9500 w/ MSI K9A2 Platinum

[JumpingJack]

Yeah Jack, the (110) PMOS is to be implmented at a later node because of its complexity but the ability has already been proven without even the need of HK/MG, some very good SOI performance has already been obtained as noted above. HK/MG will only add more benefits such as PMOS Idsat increase, after the 45nm fabrication process is matured, the integration will begin. I don't think we can judge PMOS performance based on NMOS performance data since Intels 45nm NMOS Idsat boost was only ~12% but PMOS was a huge ~50%. However the CMOS performance IIRC is not like Intels HKMG 45nm and without HKMG. The last research studies and papers on IBM/AMD SOI 45nm CMOS without HKMG is what I believe Shanghai will be based on, maybe a little tuned but not much more: PMOS 840μA/μm DC and NMOS 1240μA/μm DC at Vdd=1.0, Ioff=NA: http://hasan.nayfeh.googlepages.com/...ology_2006.pdf

Yeah, see my edit above. Si(110) is still in the research phase from my impression , simply built upon thumbing through articles -- I have not spent inordinate amounts of time reading every paper.

But looking at the experimental data ... it is quite impressive. The 1 uA/um Ion is taken at 100 nA/um Ioff is right there with Intel's current 45 nm.... the question is how close to moving from lab to fab is it? Not sure.

ITSA has not really published PMOS data, only one of two reasons a) they don't have anything to publish or b) it is so phenomenal they don't release the information for competitive reasons.

EDIT: Yeah the 45 nm data you linked here is kinda old data, in fact, it is showing about equivalent to current 65 nm process... this has been improved by now as seen by the NMOS data, so I take that 2006 info with a grain of salt (not the quality of the data, just the applicability).

EDIT2: Another thing caught my eye, you are right, PMOS and NMOS come down differently. The 50% gain you quote here is a massive jump related more to solving poly depletion problems by going metal. This is the largest node over node gain I have seen through IEDM. I think 50% is asking a lot from conventional poly (assuming no 110 -- that, again was impressive).

Edit 3: I went back to find the VLSI symposium data that yielded the NMOS numbers, it was leaked in Jan of 07, presented in june of 07. The Reg leaked it:

http://regmedia.co.uk/2007/01/28/ibmhighk.pdf

So even that NMOS data is old.

Jack