Phenom 9500 w/ MSI K9A2 Platinum

[KTE]

1.4v KTE...

Which BIOS was this?

Like many k9a2 + Phenom b2 owners, I have been requesting MSI to include the NB multiplier to a new BIOS release...here's the reply got today...

I asked them how come it was available in earlier bios versions and is/was instability the reason they took it out in succeeding ones....now i feel like i've got a hampered processor...and a motherboard...

Yeah I figured this was the problem from earlier. I know this is why they took it down and this is why they made V2 but even that didn't correct it, it was a hardware fault. So if you tried 113 BIOS, although it did allow NB FID changing, it was very buggy and restricted clocking. I have not seen any board BIOS which works flawlessly with just these basics yet, they're having too many problems. here's hoping the nForce boards can get things much better, but true, I feel ya pain.

Yeah, see my edit above. Si(110) is still in the research phase from my impression , simply built upon thumbing through articles -- I have not spent inordinate amounts of time reading every paper.

But looking at the experimental data ... it is quite impressive. The 1 uA/um Ion is taken at 100 nA/um Ioff is right there with Intel's current 45 nm.... the question is how close to moving from lab to fab is it? Not sure.

From looking at Dr. Hasans research and papers (one of the chief scientists heading IBM/AMD 45nm technology) it looks to be a 32nm implementation and not until then, they don't have the mass tooling required either. They've gone past the first phase of research, process, initial product test but not far past that that I know of. It's certainly a future target.

ITSA has not really published PMOS data, only one of two reasons a) they don't have anything to publish or b) it is so phenomenal they don't release the information for competitive reasons.

c) could also be the exact opposite of b) as we saw with AMD K10h "hushness".

EDIT: Yeah the 45 nm data you linked here is kinda old data, in fact, it is showing about equivalent to current 65 nm process... this has been improved by now as seen by the NMOS data, so I take that 2006 info with a grain of salt (not the quality of the data, just the applicability).

I've just checked again, it seems I've got two or more papers mixed up from 2006 and 2007 on 45nm. The ones I initially read were of late 2007 detailing 45nm SOI CMOS results. Just checked and those values are the same as what ITSA claimed in 2006, but the 2007 DC NMOS Idsat is 1240 uA/nm.

EDIT2: Another thing caught my eye, you are right, PMOS and NMOS come down differently. The 50% gain you quote here is a massive jump related more to solving poly depletion problems by going metal. This is the largest node over node gain I have seen through IEDM. I think 50% is asking a lot from conventional poly (assuming no 110 -- that, again was impressive).

Agreed, no way SOI CMOS without HKMG would boost p-FET Idsat by 50% over, you'd need a "special" change for that such as HKMG. Usually we are talking +100-150 uA/nm at the same Ioff and Vdd maximum being a healthy increase down a full node.
I'll link you any updated 45nm SOI PMOS data once I become aware of them.

BTW check my 2x1GB 5-4-4-5 540 2.096v on P35 fully stable guys:



Awaiting to now compare how it goes on a Phenom/X2.