Quote Originally Posted by savantu View Post
A shared L3 between 4 cores means highly complex arbitration mechanism ( that equals increased latency ).Look at AMD's K10 L3.Nothing to brag about either.It is slow , very slow.

With such small L2s , how can they feed a highly complex core with 2 threads ?? Multiple threads means cache thrashing , small size amplifies that and you have a slow L3 behind it.
If that's a good cache subsystem , I'm stupefied.It goes against everything Intel has done lately ( large , shared , extremely fast L2s which thrashed IMC equipped CPUs ).

What about the FSB ? DP Nehalem uses QPI , that works at speed of up to 4.8GTs.How does CPU-Z read that ?
This is more rubbish.

You've been more than corrected on the other forum you took this FUD too:

http://investorshub.advfn.com/boARDS...ge_id=26502149

Amazing ignorance.