Quote Originally Posted by cpuz View Post
Hey guys,

This screenshot is not fake. Now, this does not mean that cpuz is reporting all correctly, of course (Core VID is mentionned when the core voltage was not obtained from sensor chip, then cpuz displays the CPU VID).

Concerning caches on Nehalem : the L3 is now shared between 4 physical cores, meaning that is offers 4 access ports. The most access ports a cache has, the slowest it is. Consequently, it is not surprising that Intel added four small, fast and dedicated (and unified) L2 between the L1s and the L3. These caches keep using an inclusive relationship, so of course this means that the useful size of these L2s is only 128KB. However, those caches are not designed for high success rates but for speed.
CPU-Z is wrong on L1 Data size however, they should be 4x32 KB and not 4x16KB. And I don't know about FSB.
A shared L3 between 4 cores means highly complex arbitration mechanism ( that equals increased latency ).Look at AMD's K10 L3.Nothing to brag about either.It is slow , very slow.

With such small L2s , how can they feed a highly complex core with 2 threads ?? Multiple threads means cache thrashing , small size amplifies that and you have a slow L3 behind it.
If that's a good cache subsystem , I'm stupefied.It goes against everything Intel has done lately ( large , shared , extremely fast L2s which thrashed IMC equipped CPUs ).

What about the FSB ? DP Nehalem uses QPI , that works at speed of up to 4.8GTs.How does CPU-Z read that ?