Intel's First Nehalem Cpu-Z Pic.

[hollo]

2 threads through a 256kb cache?
maybe they decided single threaded performance wasn't the highest priority for this architecture.. or maybe there's been a significant latency improvement with the 45nm process... because 1 thread through 256kb is a bottleneck on l2 caches as we know them, let alone 2 threads.

it's sad for single-threaded performance, but
programs that need high performance have to be multithreaded to get it these days

The numbers given by CPU-Z kinda makes sense to me from the insignificant sources I have.

To me, it wouldn't make sense to test both QP and a new architecture together at present time, as they are both independent technologies. Could be me, but testing QP with a proved CPU + testing Nehalem with a proved FSB / connection is sensible. When both are satisfactory in terms of expectations, then the tests of combining them could begin. Just don't makes sense to test multiple new technologies all at the same time, as problem / error finding complexity increases.

Just speculating, of course, as I really don't have any insights into how the protocol is for testing these kinda of things.

could be, the nehalem demo'd at IDF was in LGA775 package so nehalem on front-side-bus definitely exists http://www.theinquirer.net/en/inquir...lem-pixellated