Intel's First Nehalem Cpu-Z Pic.

[savantu]

Regarding its authenticity I was thinking...

Since this is the first chip from Intel with an Integrated Memory Controller, the cache sizes they have currently arent needed (just look at AMD's current lineup and lack of 6+mb of cache).

That's not true.

IMC doesn't eliminate the need for a good cache subsystem.The winning combination is to have both : good caches and IMC.Good caches are needed for scalability.That's why server chips feature large amounts of cache.

AMD did not use large cache because of die sizer and engineering constraints.Intel OTOH had excellent caches and their density allowed to be implemented in large variants.

If the cache size is true , it means core complexity increased to such an extent in Nehalem that it was impossible to field a large L2 and still keep a reasonable die size ( < 300mm^2 ).