Intel's First Nehalem Cpu-Z Pic.

[savantu]

Nehalem has an IMC version, and one thats still going to use a NB as far as I have read.

Well , both have IMC , one will use NB ( QPI enabled ) and one won't.See my previous post.

I'd like to comment a little on the low L2.If the picture is true , then Holy Jesus!That's utterly different from what I expected. ( 64KB L1s and 8MB shared L2 )

I'd wager that the small 256KB L2 isn't a typical L2 as we know it. ( Instruction+Data ).I'd say if the photo is true , the L2 is an L2I or instruction cache ( holds only instructions , not data - that approach was done on Montecito Itanium , the L2 there is split into 1MB L2I and 256KB L2D ).
The L3 should be extremely fast , like on Itanium ( 14-20 cycles , that's L2 territory ) and data should go directly to the L1.The L1s need to be extremely fast too.

What are the implications if all the above are true : low frequency scalability.As for performance, it's strange.I doubt this cache structure is superior to that of Core , in fact I'd say it is inferior.