CPU PLL Voltage:
As FSB and other frequency adjustments are made and termination settings adjusted to compensate for noise in the voltage lines the CPU PLL may become out of balance. To compensate for higher FSB overclocks the PLL voltage must be adjusted upward accordingly. This is a hit or miss adjustment which will require fine tuning. For more on PLL see the excerpt below:
Quote:
Frequency synthesizers use PLLs to generate frequencies from reference sources. Although some PLL-based systems use more than one reference, a system can generate multiple frequencies from a single reference. For example, one Cypress CY2291 clock generator replaces many traditional metal-can oscillators on a PC motherboard. This replacement results in a significant reduction in board space and cost. Rarely does an external oscillator generate the reference frequency; instead, a crystal connected to the synthesizer usually supplies the reference frequency.
Figure 1 shows a block diagram of a PLL. Note that the PLL offers two types of correction. The first type is a frequency correction for large differences between the reference and feedback inputs. Applying power to the frequency synthesizer or significantly changing the feedback frequency activates frequency correction. The second correction is a type of fine tuning based on phase corrections.
VCO stands for voltage-controlled oscillator, P is a multiplier in the feedback path, and Q is a divider in the reference path. The phase/frequency detector detects differences in phase and frequency between the reference and feedback inputs. The device generates compensating up and down (increase- and decrease-frequency) signals. If the feedback-input frequency is less than the reference frequency, the pulse width of the up signal is greater than that of the down signal; if the feedback frequency is higher than the reference frequency, the pulse width of the down signal is greater than that of the up signal. These control signals pass through a charge pump and a loop filter to generate a control voltage that feeds into a VCO. The frequency of this oscillator depends on the VCTRL input. At steady state, the VCO frequency is:
FVCO=FREF•(P/Q).
The output frequency of the PLL is:
FOUT=(FREF•P)/(Q•N),
where FVCO=VCO frequency, FREF=reference frequency, P=multiplier (in the feedback path), Q=divider (in the reference path), and N=post divider.
Originally Posted by CyberDruid
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i7 920@2.8 
X3220@3.0
X3220@2.4 
E8400@4.05 
E6600@2.4
.
400FSB here 24.7(with 8 multi), 450 or so for benching and showing off 
Saaya yupp, I agree
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