ehh, I don't know about that. Each die has it's own l2 for intel's quads.

But that's not a major issue. What is a major issue is that amd positioned the l2 cache in the center of the die so it has a short pipeline and thus has uber low latency. Problem is, the l3 is positioned between 11 friggin layers of metal, so it takes the signal more time to get there, thus the higher latency