http://www.informationweek.com/news/...leID=199501467
In terms of on-chip features, the four cores of Barcelona are expected to each have their own, 512-kB L2 cache, and to share a 2-MB L3 cache. The processor will support a fast, DDR2/DDR3 memory interface.
anyone know the validity of this statement (on page 2), refering of course to the IMC supporting both DDR2 and DDR3