Quote Originally Posted by informal View Post
I think you are wrong as for the OC part.These chips will be easier to OC than X2s based on K8.SInce the L3 and IMC reside on the one and the same power plane,one can set it to higher/lower clocks(and in full async. from the 4/2 cores) in order to get the highest OC possible with good cooling.
Actually, I think the split power plane will make it harder.... but now it is becoming clear, I think TechARP may have misprinted, it makes more sense that the L3 will fix withrepect to the IMC (northbridge) fequency and that will vary with the frequency divider necessary to drive the memory.

In terms of OCability, this may or may not be true.... the details of how AMD has implemented the L3 cache is sketchy now based on your link.... if they are adjusting the number of L3 cycle latency dynamically (as you interpret), this means that they are adjusting to keep the L3 cycle latency at the border edge of the physical time it takes for signalling L3... if this is true, overclocking will crap out the L3 very very early. This is why I wonder if they will provide BIOS writers (or should I say BIOS writers provide us) with the ability to adjust the L3 latency cycles.