AMD cuts to the core with 'Bulldozer' Opterons

[terrace215]

Each interlagos processor can run either 8 256-bit executions per cycle or 16 128-bit executions per cycle.

In newer AVX-updated code, we will have the same number or executions as Intel. In older non-AVX code we will have 16 128-bit executions to their 8 128-bit executions.

When speaking of Interlagos compared to Intel, it seems a bit silly to assume they won't avail themselves of the same trade-off that Interlagos uses to put up big throughput numbers, should they find its market compelling: taking advantage of the fact that power is non-linear with frequency, particularly at the top end. So you can drop the clock ~30%, and double the number of cores while remaining at the same power.

Intel can produce a 12- or 16-cored low-voltage/low-power Sandy Bridge, either directly, or with the yield- and cost-effective two-die MCM approach, and thereby take advantage of this same, almost completely design-agnostic principle.

So I think more focus on the non-MCM, baseline Zambezi/Valencia capabilities would be more likely to both illuminate the strengths and weaknesses of BD's *design* as well as let us properly gauge its true competitive position vs Intel's offerings.

(I'll grant you that as Magny is also an MCM/(low-speed/double-core), Interlagos vs Magny changes do result from BD design features.)

[JF-AMD]

Well, here is how I understand it. We have 2 128-bit FMACs that fuse into a 256-bit AVX. Intel "double pumps" a 128-bit unit to get it to 256-bit (I think Hans has a die shot that shows the SB 256-bit being about the same size as the current 12-bit.)

As it has been explained to me, the double pumping requires AVX, meaning that if the SW does not support AVX, then things execute at 128-bit only.

Perhaps someone with some info could chime in.

[accord99]

arent thuban allready a win in perf/mm2/watt ???? so i would expect the same trend to keep going at amd

No, i7 Lynnfield uses less power, is faster in anything with less than 6 threads, roughly comparable with 6+ threads and has a smaller die size.

[savantu]

Each interlagos processor can run either 8 256-bit executions per cycle or 16 128-bit executions per cycle.

That's 8x4=32DP FLOPs, like I've said if I understand correctly. 8 FP clusters, each capable of 4 DP FLOPs.

In newer AVX-updated code, we will have the same number or executions as Intel. In older non-AVX code we will have 16 128-bit executions to their 8 128-bit executions.

How many cores do you assume for Intel ? Only 4 ?

Core/Nehalem do 2 128 bit executions per cycle now , with 6 cores ( Westmere ) we have 12 for CPU and with Beckton/Eagleton we have 16 and 20.
This brings another interesting point : without AVX, Interlagos won't be faster than MC in FP operation. MC can do 2x128bit execution per cycle x12 cores => 24 per CPU . Of course, that's a theoretical max and it is likely that BD will have a far higher utilization of those resources with a multithreaded front-end and a shared FP cluster.
Interesting anyway.

[JF-AMD]

Hans answered you earlier, there are 16x4, not 8x4.

[Chumbucket843]

Well, here is how I understand it. We have 2 128-bit FMACs that fuse into a 256-bit AVX. Intel "double pumps" a 128-bit unit to get it to 256-bit (I think Hans has a die shot that shows the SB 256-bit being about the same size as the current 12-bit.)

As it has been explained to me, the double pumping requires AVX, meaning that if the SW does not support AVX, then things execute at 128-bit only.

Perhaps someone with some info could chime in.

double pumping basically cuts the delay of the execution stages on half. this means double the clockspeed so whether the code uses 128bits of the avx registers or all 256bits execution will be two times faster (in theory). BD will do double operations/clock and SB will double clockspeed, two ways to solve the same problem.

i really dont think that they will use double pumping, hyperpipelining, or whatever you want to call it in sandy bridge. it caused a lot of issues in netburst. to put it simply making alu's clock 2x faster is very complex, it takes experienced designers and many circuit simulations to assure robustness. it is much more productive having these people work on other parts of the chip, like designing a really fast L1 cache, high speed I/O, or power/clock gating.

[Opteron146]

i really dont think that they will use double pumping, hyperpipelining, or whatever you want to call it in sandy bridge. it caused a lot of issues in netburst. to put it simply making alu's clock 2x faster is very complex, it takes experienced designers and many circuit simulations to assure robustness. it is much more productive having these people work on other parts of the chip, like designing a really fast L1 cache, high speed I/O, or power/clock gating.

Just read Hans' post here:

Note that the way Intel implements 256 bit AVX is somewhat of a trick to
avoid bloating up the core to much. They actually used a 128 bit unit which
runs at double the clock speed because they "hyper-pipelined" it .

The FP/SSE/AVX area on the Sandy Bridge die is only slightly greater as
the FP/SSE unit on Westmere. It does have consequences for the power
consumption however and Sandy Bridge will be about as large a single
Bulldozer module anyway.

http://www.amdzone.com/phpbb3/viewto...rt=875#p185515

It has to be hyper pipelined, because the FPU is nearly unchanged from Westmere's but - according to intel - it should be able to handle 256bits in 1 clock. Thus the FPU has to be double clocked. Plain logic.

If you deny it, then you have to point out the 256bit units on SB's die plot.

cheers

P.S: Who else if not intel has "experienced designers" ? ;-)

[terrace215]

i really dont think that they will use double pumping, hyperpipelining, or whatever you want to call it in sandy bridge. it caused a lot of issues in netburst. to put it simply making alu's clock 2x faster is very complex, it takes experienced designers and many circuit simulations to assure robustness. it is much more productive having these people work on other parts of the chip, like designing a really fast L1 cache, high speed I/O, or power/clock gating.

While this is true, what do you say to the die photo analysis? There's also been an interesting comment by an Intel guy, here:

http://software.intel.com/en-us/foru...ad.php?t=68554

It seems point 1) may have assumed it requires monolithic 256-bit hardware to achieve 1 cycle throughput for 256-bit AVX instructions. That's not true.

Vague, but perhaps a hint?

[informal]

The way I see it is that intel fellow indirectly confirmed what Hans already found out from SB die photo.

[Chumbucket843]

keep in mind i am just giving my opinion. from a risk/reward perspective it just doesnt seem like a good decision, then again it is intel.

also better floorplanning could easily increase FETs/mm2.

http://yfrog.com/49iacores2p
here is a comparison of intel's cores. they are normalized by height. you can see that the datapath in the upper right keeps getting proportionally smaller until sandy bridge.

Just read Hans' post here:



http://www.amdzone.com/phpbb3/viewto...rt=875#p185515

It has to be hyper pipelined, because the FPU is nearly unchanged from Westmere's but - according to intel - it should be able to handle 256bits in 1 clock. Thus the FPU has to be double clocked. Plain logic.

If you deny it, then you have to point out the 256bit units on SB's die plot.

cheers

P.S: Who else if not intel has "experienced designers" ? ;-)

no one can point out sb's alu's. individual units have been invisible to the naked eye for many years now.

yes, intel has experienced engineers but not enough. also they need to use them effectively due to their scarcity.

[terrace215]

The way I see it is that intel fellow indirectly confirmed what Hans already found out from SB die photo.

It seems likely. (edit: although, hmm, chum makes an interesting point ^^ there ^^ )

Of course, as I argued above, the real comparison should be between an 8-core Sandy Bridge and an 8-core Valencia/Zambezi, if you want to look at relative design strengths.

If you instead insist on comparing to Interlagos, what happens to that analysis if Intel says "we'll play that same trick, too" ? (Have to give credit to JF for framing the debate this way, however. )

[superrugal]

It seems likely. (edit: although, hmm, chum makes an interesting point ^^ there ^^ )

Of course, as I argued above, the real comparison should be between an 8-core Sandy Bridge and an 8-core Valencia/Zambezi, if you want to look at relative design strengths.

If you instead insist on comparing to Interlagos, what happens to that analysis if Intel says "we'll play that same trick, too" ?

Compare at the same price, otherwise it will be meaningless. So we have to wait, or starting a discussion about the manufacturing cost of 32nm.

[informal]

Intel would first have to put that thing on the roadmap and then play that game . And as things are right now,there is not even a hint of such a design. 2 years per design cycle and maybe in 2012 we can see such a product. I don't think that current server socket that will host SB EX can support 2 SB dice linked via QPI.

[Opteron146]

no one can point out sb's alu's. individual units have been invisible to the naked eye for many years now.

No you can, e.g. compare AMD's FPU from K8 -> K10. It was more or less doubled, because it was increased from 80bits -> 128bit. Very easily visible.
The same should be the case if Intel would double their FPU from 128 -> 256b.

But you cant see anything like that. The new FPU is just a tiny little bit bigger than Westmere's old 128bit FPU. Definitly not enough to handle "real" 256bits.

However the double clocked FPUs could be a good solution, too.

Let's wait and see.

[terrace215]

keep in mind i am just giving my opinion. from a risk/reward perspective it just doesnt seem like a good decision, then again it is intel.

also better floorplanning could easily increase FETs/mm2.

http://yfrog.com/49iacores2p
here is a comparison of intel's cores. they are normalized by height. you can see that the datapath in the upper right keeps getting proportionally smaller until sandy bridge.

Those are.. 65nm conroe, 45nm nehalem, 32nm westmere, 32nm SB, from left to right?

So, err... the last transition not being a shrink doesn't explain this?

[terrace215]

Intel would first have to put that thing on the roadmap and then play that game . And as things are right now,there is not even a hint of such a design. 2 years per design cycle and maybe in 2012 we can see such a product. I don't think that current server socket that will host SB EX can support 2 SB dice linked via QPI.

The MCM approach is only for yields / costs. And that would not take 2 years, and who's to say they aren't already at work on it?

Just bumping the number of cores would be the more expensive, less design-work way to do it. Surely you don't think *that* would take them all that long, given the plethora of SB variants already coming?

[terrace215]

Compare at the same price, otherwise it will be meaningless. So we have to wait, or starting a discussion about the manufacturing cost of 32nm.

The one-time CPU cost is a small fraction of the total system-over-time cost.

[JF-AMD]

But Intel does not have an 8-core client, so you can't compare an 8-core SB to an 8-core Zambezi.

Just compare client to client, and server to server. Choose the same price points and it is off to the races.

[JF-AMD]

The MCM approach is only for yields / costs. And that would not take 2 years, and who's to say they aren't already at work on it?

Just bumping the number of cores would be the more expensive, less design-work way to do it. Surely you don't think *that* would take them all that long, given the plethora of SB variants already coming?

Right now if you look at the 2P and 4P intel products (not counting itanium) you have 2 2P architectures (5600 and 6500) and you have 1 4P (7500) with a rumored second one.

Now, throw an MCM in the mix, and even if Intel wants to build it, it will create a mess of their roadmap and the OEMs probably wouldn't want to use it.

Just because they can build it doesn't mean that everyone will buy it.

Too many platforms, too many sockets, too litttle differentiation. They're smarter than to try that.

[terrace215]

But Intel does not have an 8-core client, so you can't compare an 8-core SB to an 8-core Zambezi.

Just compare client to client, and server to server. Choose the same price points and it is off to the races.

Valencia, then, I can't keep track of all your crazy names. Is that one the 8-core server part?

Price points for the server CPUs only have little to do with things, as you know.

----

As for client, has it been completely resolved whether client high-end SB will be only 6-core, or 8-core, or offered in both 6- and 8-core? I haven't heard this before.

[terrace215]

it will create a mess of their roadmap and the OEMs probably wouldn't want to use it.

Just because they can build it doesn't mean that everyone will buy it.

Too many platforms, too many sockets, too litttle differentiation. They're smarter than to try that.

Err, you'll have to do better than that, lol.

Same platform, same socket, seems like a fair bit of differentiation to me...

Yes, how on earth would the market survive if, in addition to a high-speed 8-core part, they also offered a medium-speed 12- or 14-core "continuous throughput optimized" part...

If it wouldn't, well then clearly your Interlagos part will just ruin the market for Valencia, now won't it?

It's the same principle: slow the cores into the most power-efficient speed-band, and add more cores on the same part. You guys used this trick with MC, and plan to continue with Interlagos. What's good for the goose is good for the gander, no?

[mongoled]

** sorry 4 the off topic **

wow just wow, we have had a good 2 pages of excellent constructive dialect with regards to Bulldozer architecture



Keep the love flowing, lol

[-Sweeper_]

But Intel does not have an 8-core client, so you can't compare an 8-core SB to an 8-core Zambezi.

Just compare client to client, and server to server. Choose the same price points and it is off to the races.

there will be 8-core SB for desktops @ socket LGA2011

be sure intel doesnt want to share the enthusiast client market

[terrace215]

there will be 8-core SB for desktops @ socket LGA2011

be sure intel doesnt want to share the enthusiast client market

Can you confirm that this mysterious (LGA-1356) intermediate socket (between LGA-2011 and LGA-1155) has been (wisely, IMO) ditched in favor of LGA-2011 for the high-end desktop client as well?

[Hornet331]

If S1356 is gone, say hello to 400€+ boards with the top of the cream going for 500€