Radeon HD 7000 Revealed: AMD to Mix GCN with VLIW4 & VLIW5 Architectures

[DilTech]

Remember, AMD never "scaled" their cache, ROP and memory hierarchy like NVIDIA did. With NVIDIA all three were tied together due to the nature of their core architecture but AMD could always scale them in an asymmetric fashion.

For example, the Barts LE core used on the HD 6790 1GB disabled two of the Render Back Ends of the Barts core to produce a card with a 256-bit memory bus but only 16 ROPs (rather than 32). As such, PAST AMD cores weren't tied down in the same way as NVIDIA's Fermi architecture.

That's going with the 4 split rather than the 8 split, still matches the mathematics we've always seen. They didn't disable RBE's, they disabled half of the Rops per RBE.

I seriously can't even remember the last time we saw a gpu that wasn't symmetrical rop to memory controller. In fact, I'm now curious... When IS the last time AMD/ATi released a chip that wasn't? (serious question) AFAIK both brands ARE actually tied together in this aspect presently.