Quote Originally Posted by DilTech View Post
Rops are tied to the memory controller, in blocks of 4-8 rops per memory bus channel (usually 8 these days). 32 rops would be either a 256bit bus or a 512bit bus. For 384-bit it'd either be 24 or 48 rops. You can't divide 32 rops evenly to make said 384-bit bus, and as such it's probably fake just based off of that alone.
Remember, AMD never "scaled" their cache, ROP and memory hierarchy like NVIDIA did. With NVIDIA all three were tied together due to the nature of their core architecture but AMD could always scale them in an asymmetric fashion.

For example, the Barts LE core used on the HD 6790 1GB disabled two of the Render Back Ends of the Barts core to produce a card with a 256-bit memory bus but only 16 ROPs (rather than 32). As such, PAST AMD cores weren't tied down in the same way as NVIDIA's Fermi architecture.