SSD Write Endurance 25nm Vs 34nm

[zads]

I'm not certain of the point of this thread's experiment, but I'm glad it has brought some good technical discussion to the board.

...This is of course similar to the problem that hard drives are having at the moment with their increasing areal densities. As areal density goes up, signal to noise ratio goes down and 512 bytes per sector is no longer enough to contain all the ECC bits they need to correct the increasingly frequent errors.

Well written technical statements here, I would only nitpick at the last statement, correcting it to:
"...512 bytes per sector is no longer efficient to contain all the ECC bits they need to correct the increasingly frequent errors."
The analogous continuous increases in page size in NAND flash dies is due to the same reason.

...As for "order of magnitude", no, not if you mean a factor of 10, as that phrase usually means. When the 3Xnm flash first came out, 5000 erase cycles was not uncommon. With the 25nm flash from IMFT, I have heard both 3000 and 5000 erase cycles. So unless you are claiming that the physics dictate that the erase cycles from 34nm to 25nm must go from 5000 to 500, it is not an order of magnitude. Besides, the 3Xnm flash currently has numbers ranging from 3000 to more than 10,000. You know why? Process improvements and binning. The SSDs usually get the best chips from the wafer. The lower quality chips go to less demanding applications, like USB sticks and consumer electronics like cell phones or media players.

Process improvements and binning is about right- in terms of 25nm MLC:

Temperature rating:
Industrial temp parts- highest quality/price (1 order of magnitude better BER than commercial)

Endurance:
eMLC- highest endurance/price @10k
cMLC- higher endurance/price @5k
MLC- normal bulk of retail market/price @3k
ES_MLC- early sample stuff, and gray market stuff- lowest price (unrated, but @~1.5k)

So yeah.. beware of unscrupulous SSD manufacturers that sometimes release early/new drives with crap flash inside.