Quote Originally Posted by johnw View Post
"Without testing"??? Certainly the flash memory manufacturers have extensively tested the endurance of their products. The large semiconductor manufacturers have extensive testing and reliability procedures for products both in development and production.
This is not in dispute actually. I meant published testing. Not in-house testing that is treated like proprietary information. I have little doubt that they know the actual limits of their technology. Those numbers may not make it into their spec sheets however depending on whether the numbers put their products in a positive or negative light. They are in business to make money and can be expected to act in a way that is consistent with that. IOW, their data can be expected to have a strong bias in their favor at all times.


There are flash memory spec sheets available from, for example, Micron. I haven't jumped through their hoops to sign up and be able to download their spec sheets on their flash memory, but if you are so concerned about this issue, I am surprised that you have not.
Again, their numbers cannot necessarily be trusted to reflect real world experience or real world unbiased testing. However I will see if I can get my hands on some of those spec sheets.

As for your "estimates" of erase cycles, I'll take the spec sheet from a large flash manufacturer over your "estimates" every time.
My estimates? They are just the typical estimates that I have read from many sources over the years. Read any IEEE article on the subject and you will see similar numbers. They are just ballpark afaik however. Hence the usefulness of this testing.

Semiconductor engineers are clever -- if they have to meet, say, 3000 erase cycles for a smaller process, they will usually find a way to do it. Process tweaks and optimizations, better equipment, testing and binning, etc.
I have no doubt there are optimizations and tricks that might lead to improvements in write endurance, but what you are implying is an order of magnitude improvement. Those sorts of improvements do not come easily and generally require a fundamental breakthrough that would typically be trumpeted from rooftops. Not the proprietary advancements themselves of course, but some general idea of what they did. They might even apply for a patent.

Write endurance in NAND flash is fundamentally limited by a breakdown in the thin silicon dioxide or oxide nitride oxide (ONO) dielectric layer(s) dividing the floating gate from the rest of the transistor (mainly the p-substrate). That breakdown is caused by the cycling electric fields used for program/erase. The process is not fully understood, despite having been studied for decades, but it may have something to do with electrons getting trapped in the SiO2 dielectric (trap-up) while quantum tunneling through it during application of program or erase voltages. Over time those electrons can form a conductive path through the dielectric. At least that's one theory of SILC (stress induced leakage current). The trapped electrons may also slow the tunneling current to the point that not enough charge gets transferred during the program or erase voltage application and Vt (threshold voltage) changes to the point that it represents a different binary state. Another theory states that positive charge gets trapped in the tunnel oxide when the silicon and oxygen from the SiO2 are separated. The oxide breakdown is accelerated by higher voltages and higher temperatures. As the transistors get significantly smaller with each process shrink the dielectric area for each transistor also gets smaller. You have the same electric field stresses over a smaller area. So the probability of the SiO2 going bad over time is greater on a per cell basis, despite the fact that when looked at over the entire array the probability is the same.

Smaller transistors are also more sensitive to fluctuations in the number of electrons stored in the floating gate. With SLC cells this isn't so bad, but for MLC it makes things quite difficult, especially as the transistor ages and wears. With 2 bit MLC you have a low, intermediate-1, intermediate-2, and high voltage state that represents (binary) 00, 01, 10, and 11. As the process size gets smaller fewer and fewer electrons stored in the floating gate determine whether you are at, say, intermediate-1 or intermediate-2. This increases your BER (bit error rate) and requires more bits of EDC/ECC to correct it. This is of course similar to the problem that hard drives are having at the moment with their increasing areal densities. As areal density goes up, signal to noise ratio goes down and 512 bytes per sector is no longer enough to contain all the ECC bits they need to correct the increasingly frequent errors.