Quote Originally Posted by gojirasan View Post
The old write estimates for that process size were around 1500 p/e cycles, but of course neither company is going to be using those estimates. Instead the write endurance estimates are exactly the same as for 25nm cells. What that shows is not that these companies can get around the laws of physics, but that, without testing, they can claim anything they want which serves their marketing purposes.
"Without testing"??? Certainly the flash memory manufacturers have extensively tested the endurance of their products. The large semiconductor manufacturers have extensive testing and reliability procedures for products both in development and production.

There are flash memory spec sheets available from, for example, Micron. I haven't jumped through their hoops to sign up and be able to download their spec sheets on their flash memory, but if you are so concerned about this issue, I am surprised that you have not.

As for your "estimates" of erase cycles, I'll take the spec sheet from a large flash manufacturer over your "estimates" every time. Semiconductor engineers are clever -- if they have to meet, say, 3000 erase cycles for a smaller process, they will usually find a way to do it. Process tweaks and optimizations, better equipment, testing and binning, etc.