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[Apokalipse]

It's AMD's definition, you have simply accepted it.

Not just AMD's.

Try and find me a computer science source that agrees with that definition. You won't, because before now because instruction fetch and retire were traditionally considered part of the core.

They still are with BD modules.
You do have two sets of fetch, retire operations occurring in the one module simultaneously.
Yes it does it with shared hardware. But it still functions the same way as two cores, with the only exception being that specific 256b instructions can span two cores (by being decoded into 2 x 128b micro-ops).
Which is NOT like hyperthreading. It's exactly the opposite ("reverse hyperthreading")

I agree that it is more flexible and I like that design. But being flexible doesn't mean that it is really two separate FP units.

Being able to process two threads simultaneously without sharing pipelines does.

Take away one half and it wouldn't be able to process 256-bit instructions.

Yes it CAN process 256-bit instructions even with one 128-bit pipeline.
256-bit AVX instructions are decoded into 2 x 128-bit micro-ops anyway. That's how it's able to span across two 128-bit FP pipelines (and they are separate pipelines). They don't process a single 256b micro-op.

With separate schedulers, it would just mean always taking two cycles to process each 128-bit micro-op (one half of the 256b AVX instruction) in the one pipeline.

With a shared scheduler. it means that not only is it possible to process both 128-bit micro-ops in one pipeline (in two cycles), it's also possible to process them in two 128-bit pipelines (in one cycle).
Hence "reverse hyperthreading"

It is designed to be ganged together to process them. One half can't do half a 256-bit instruction in two steps, that would require a redesign of the FP unit.

Yes it can. And does even with the shared scheduler if one FP pipeline is busy.