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[Apokalipse]

That's just your definition however. One could just as easily say that a core is everything from instruction fetch through instruction retire.

It's not just my definition.
Also, each core in a BD module can and does do its own fetch and retire with its own thread.
Yes, it uses shared hardware to do it. But it still works that way.

Even by your definition it wouldn't be two full cores because it isn't two full floating point units.

Yes it is.
Sharing the FP scheduler (capable of handling two threads of FP micro-ops simultaneously) is just more flexible than two independent schedulers, AND uses less transistors.

It is one FP that can do work for either "core". Take away one half of that and the CPU couldn't compute the full instruction set.

Yes it can.
It just means it has to take two cycles to process each 128-bit micro-op of a 256b AVX instruction.
Actually, BD still can do it that way even with the shared FP scheduler - if one FP pipeline is busy, it can send both 128-bit micro-ops of the 256-bit AVX instruction through one 128-bit pipeline. It just takes two cycles instead of one.

In short, it is not really "1.5 cores". It is 2 cores with a kind of "reverse hyperthreading" for specific 256b FP instructions that can span across two cores, implemented by sharing some hardware, which also saves transistors.