Originally Posted by danielkza 8 cycles @ 800MHz (the command clock is not doubled like the data rate) = 10ns 9 cycles @ 933Mhz = 9,65ns So 1866 wins in both absolute latency and bandwidth. But better than teorizing is running some benchs yourself. Thank you very much, but I don't get stable 1866 9 10 9 28 2T I test with 1,1 VCCIO and 1,5625 VDIMM and nothing helps. Prime cause bsod at seconds to begin. (Sorry for my bad English)
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