Bulldoze that Sandy Bridge

[savantu]

I pointed out several above and you even quoted that response. Please go back and read it.

Yes, I've read it first time. As I've said then, the features you mention are found in all dies, in some they are active in others they are not.
That does not make it different designs.

I'll tell you for the third time here to look again.

Look at the edge of each picture. What is on the outer edge of each die is NOT the same, not at all.

Maybe I can't see the picture because of the trees, but frankly, except the blurring and different color tones, to me they seem identical.
Feel free to point with an arrow where you see the differences please.

They have different pinouts, even.

What has pinout to do with the design ? Do you think a K8 on socket 939 is different from a K8 on socket 940 ?
Or Prescott on socket 478 was different from a Prescott on socket 775 ?

I heavily doubt 1207 & C32 are somehow, magically pin compatible with AM2+/AM3.

What I'm arguing has nothing to do with compatibility. I thought it was obvious.

Fact is, Istanbul made it to the market long before Thuban. So by your own logic, Thuban =/= Istanbul.

Which reinforces the point. If server made it out before desktops, it means it has no extra features which needed more time to be implemented and validated. It was just a matter of marketing; supplying the highest margin market segment until production ramped up and desktops could be supplied.

So far, only the E0 stepping chips have turbocore (AMD has had per core clock modulation based on workload since Agena, mind you ), an "anti-Agena CnQ" setup, in a twisted sense. Yeah, try to argue they had the functionality on every AMD hexcore design. Fact is, they don't.

You don't add turbocore with a stepping. Either that functionality is there from the uarch phase, when all the control logic, power delivery and measure points were thought out, or you're in for a full respin ( the designed is changes, layouts, number of transistors, etc ).
So the point is that all hexacore had turbocore in, but wasn't enabled in all products. Either because of time-to-market restrictions or complexity, it could be validation of the turbocore feature wasn't ready when the design was thought fully functional w/o turbocore. Thus they decided to ship it with the feature disabled and when the validation is done, they enable it.

And *just* incase if you are ignorant to the fact (I'm waiting for a staunch denial...), JF-AMD is John Fruehe, AMD's Server (and a few other things) PM. And if you think Product Marketing is drawing advertisements.... then... "wow" is all I will care to say in response.

I'm fully aware of who he is. That doesn't mean he knows everything about server cpus or be completely open about all issues. Do you suppose he knows the instruction latencies in current CPUs or other really technical stuff ? I bet he doesn't. And frankly, he doesn't need to. He's not selling circuit design techniques, but functionality. He's selling performance per watt or per $, not L1 nanosecond access time.

I've met people on different forums which can eat JF for breakfast when it comes to the insides of AMD CPUs. They are SW designers, HW engineers, you name it. They know those quirks either because they need to in their daily activities or as a hobby.

Anyway, I prefer to leave the topic where it is and agree to disagree.