AMD: 32nm issues fixed

[Hans de Vries]

Thanks !

One hint:
You have two "HT link 2"s ;-)

fixed

2 questions:
a)Could your PCIe link be another HT link ? Together with the link on the opposite side it could be 6 HT links together. The link on the top right actually looks like one of the double row links of Shanghai inbetween/ behind the L3 caches:
You named it HT2 & 3 in that picture:
http://chip-architect.com/news/Shanghai_Nehalem.jpg
But maybe they just copy/pasted it .. ;-)

The area in the middle shows four times the HT logic
as well so I wouldn't expect more than 4 HT links.

b) With the "re-order buffer", do you mean the retirement queue, mentioned at rwt:
http://www.realworldtech.com/page.cf...610181333&p=10
? Or something else ?

Thx

Alex

Yes, that's the one.


Regards, Hans.