AMD: 32nm issues fixed

[saaya]

Or think it this way: if 1MB more L2 (~6mm^2) buys you 10% higher average (!) IPC for a fraction of the power you need to use in the core (and a few mm^2) to achieve the same - which of those options would you choose?

See this review comparing - besides other CPUs - a 2.8GHz 2C PhII (downclocked) with 512kB L2 per core and 6MB L3 (for 2 cores!) and a 2.8GHz 2C AthII with 1MB L2 per core and no L3:
http://www.techpowerup.com/reviews/A..._X2_240/4.html
In several benchmarks the AthII is faster.

hmmm but does 1mb really boost ipc that much?
the highest gains from bigger caches in the past ive seen were around 5%...
funny btw, instead of adding cache to a design as a "midlife kicker" its now adding cores+cache

Saaya the server BD will accomodate standard ddr3 1600 while desktop will actually suppor ddr3 1866 which in dual channel will provide over 29 gb/s bandwidth. Thats more than the tripple channel socket 1366 b/w of 25 gb/s while using its dd3 1066 officially suppported.

source: http://www.techpowerup.com/134739/AM...-Revealed.html

hah, yeah but not many people run their mem below 2000, and if they do they usually run it at tight timings boosting bw :P

Saaya,each BD Module has two full cores,each having dedicated integer pipelines and can have either 1(per core) 128bit FMAC or 256bit FMAC,depending on the workload(single or multithreaded).So you see,the cores are not half as*ed and crippled in any way,you have everything that traditional core has plus more if you run single threaded workloads(2x FP throughput with ability to execute 2 FADDs or 2 FMULs in parallel,which is not possible today per single core,in any x86 core).Shared frontend is actually a good thing,being able to make the best use of fetch bandwidth available in either of the workloads scenarios (I bet this is the key component of the effectiveness of this design,apart from the schedulers of course).

hmmm so they CAN share their fpu but dont always? but then how does this affect the definition of a core? its still two cores then, just that they CAN in some scenarios work together... right?

As for memory,BD desktop officially supports 1866 standard,so one can assume it will unofficially be able to run with RAM modules clocked much higher than that.Add on top of that a 30% IMC throughput improvement,without adding a 3rd channel,and you get a massively stronger memory throughput,which is needed with 8 stronger than Thuban cores .

well the presentation somebody posted here only mentions a 30% boost while mentioning a 20% boost in supported memory clocks... call me cynical but in my experience with presentations like this it doesnt mean 20% clockspeed resulting bw boost PLUS 30% arch resulting boost... it means 20% clockspeed resulting bw boost plus 10% arch resulting boost... BEST CASE SCENARIO

1600-1333 = 267

267/1333 = 0.20030007

so to me this is 20% ?

my bad

You sure spend a lot of time complaining about AMD. If you are so sure that our products are a flop, why bother?

cause i actually like amd, and i think you guys can do a lot better than what youve been doing in the past years...

As for the memory controller, it will have no problem feeding the cores. AMD has a long history of high performing memory controllers, you should look at the legacy of products that we have delivered to market. Then look at the fact that we are giving a 50% increase in throughput. The combination of those two alone are 2 great pieces of evidence that the memory controller will be just fine. You have no basis for your statement other than the desire to see AMD fail.

amds ddr2 and ddr3 imcs are e... no offense, but seriously... the ddr2 imc offered no advantages over ddr1 whatsoever, and the ddr3 imc had clockspeed issues from day1 and is comparable to intels P35/X38 ddr3 memory controller which is 2, soon 3 generations behind.

the only memory controller amd ever had that rocked was the a64 imc, and, correct me if im wrong, was mostly the brainchild of a single brilliant engineer, which left the company, so turning that into a "history of achievements of amd" is a pretty far stretch dont you think?

As to the caches, weren't all of the intel fanboys raving about intel's cache siszes in the past and saying that AMD caches were too small? You can't have it both ways.

you mentioned that before... ive never seen people complain about "small" caches on amd chips... not here on xs at least, people here tend to compare performance, not specs...
and when people DID complain about cache sizes, you should know that they dont complain about cache sizes, what they really want to say is "i want a faster cpu"

The problem with HT is that while it doubles the number of threads that you can handle, it does not double the number of integer execution pipelines, or, more importantly the number of schedulers. If you have only one scheduler and only one pipeline, calling to two cores would really be misleading.

thats what i said...

Each bulldozer module has 2 integer schedulers and 2 sets of integer pipelines, which is why it is defined as 2 cores. This FUD is really getting tiring.

so then why did somebody mention that with BD the definition of cores changes? thats what started the whole thing, it seems it was a misunderstanding? it made me think 2 bulldozer cores can actually only work in tandem and not chew through data on their own, which would make it ONE core and not two. several people then hooked in and disagreed that such a core would still be two cores for some reason.
i guess it was misunderstandings all over the place

Exactly. Plus, we have 1 FPU per core. We can combine them to get to 256-bit AVX. Intel combines a 128-bit FPU and the integer pipeline in order to get to 256-bit AVX. So, techincally, does that mean that Sandybridge is only a half core becasue its integer pipleine is shared with the FPU?

as long as each part CAN work fully independantly, no... as soon as two blocks are dependant on each other its ONE block... at least by my definition

thx for clarifying this

1. Everyone but you is seems to be OK with this.
2. Clock speed percentage rarely equals actual throughput percentage. I can't believe that you don't know that.
3. Every single Bulldozer core has an FPU. 16 cores, 16 FPUs. Spreading lies like you are is not helping your credibility.

1. good for them... whats it supposed to be to me?
2. i cant believe you think i dont know that, i think we both know that you know that i know it ^^
3. not my intention... the one fpu per module was a misunderstanding, my bad...

what happened to saaya lately ????

thx for contributing to the discussion

No, they are completely different cores designed by completely different teams.

but they do share the same building blocks right? some of them at least... makes sense...

IF you think that +30% is not significant, then all intel processors since Core2 are "unimpressive" ;-)

i thought we are talking about memory bandwidth, not ipc or overall performance...
if bd has a 30% ipc or overall performance boost (per core) over their current chips ill be deeply impressed :0

I meant the same think, AMD could recycle their triple channel C42 (or whatever the name is) platform, too. But even that costs money, not sure how many board manufacturers would build boards for it.
Well - it will depend heavily on the chip .. if it is fast enough, AMD would snatch lots of that small enthusiast market segment. But it will be hard against Intel's 22nm CPUs.

amd has a tripple channel platform?
wasnt it quad channel? its MCM so its two dualchannel chips on one package. and they ARE recycling that for servers and might use it for enthusiasts, though i doubt it... enthusiasts wont see benefits from the extra bandwidth i think... for enthusiasts latency is more important than bandwidth cause only few cores are actually used.

Why should nVidia's problem be of AMD's concern ? If it would have been ATi - then you could make at least a small connection .. but nVidia ?

sigh... cause they all use solder balls to connect silicon to organic packages? :P