AMD: 32nm issues fixed

[Opteron146]

inverse photoshopping effort...
Regards, Hans

Thanks !

One hint:
You have two "HT link 2"s ;-)

2 questions:
a)Could your PCIe link be another HT link ? Together with the link on the opposite side it could be 6 HT links together. The link on the top right actually looks like one of the double row links of Shanghai inbetween/ behind the L3 caches:
You named it HT2 & 3 in that picture:
http://chip-architect.com/news/Shanghai_Nehalem.jpg
But maybe they just copy/pasted it .. ;-)

b) With the "re-order buffer", do you mean the retirement queue, mentioned at rwt:
http://www.realworldtech.com/page.cf...610181333&p=10
? Or something else ?

Thx

Alex

[Hans de Vries]

Thanks !

One hint:
You have two "HT link 2"s ;-)

fixed

2 questions:
a)Could your PCIe link be another HT link ? Together with the link on the opposite side it could be 6 HT links together. The link on the top right actually looks like one of the double row links of Shanghai inbetween/ behind the L3 caches:
You named it HT2 & 3 in that picture:
http://chip-architect.com/news/Shanghai_Nehalem.jpg
But maybe they just copy/pasted it .. ;-)

The area in the middle shows four times the HT logic
as well so I wouldn't expect more than 4 HT links.

b) With the "re-order buffer", do you mean the retirement queue, mentioned at rwt:
http://www.realworldtech.com/page.cf...610181333&p=10
? Or something else ?

Thx

Alex

Yes, that's the one.


Regards, Hans.

[FlanK3r]

whau, thx Hans. What do u think as expert about clocks Zambezi chips and OC this chips?

[Hans de Vries]

whau, thx Hans. What do u think as expert about clocks Zambezi chips and OC this chips?

I'm quite optimistic, specially in regards with single thread
clock speeds that not only benefit from the reduced number
of gate delays per cycle, the 32nm HKMG process,but also
from the improved Turbo options. I don't know how much of
all this potential will be already be realized from day 1 at the
launch so i am reluctant to speculate on actual numbers...


Regards, Hans

[JF-AMD]

Hans, be sure to look me up about the time we are launching it so that we can make sure you have all of the final data.

[qcmadness]

inverse photoshopping effort...
Regards, Hans

320mm^2?

[stuffme]

To me this all looks backwards now. All the cache eats many times the core size, which made me wondering. Wouldn't it be more useful to ditch half of those caches and use the transistors to make the actual cores a lot beefier?

[saaya]

I'm quite optimistic, specially in regards with single thread
clock speeds

you got my attention

Hans, be sure to look me up about the time we are launching it so that we can make sure you have all of the final data.

To me this all looks backwards now. All the cache eats many times the core size, which made me wondering. Wouldn't it be more useful to ditch half of those caches and use the transistors to make the actual cores a lot beefier?

yeah, thats what i wondered as well... my guess is that the imc wouldnt be able to feed more than 8 cores, and its already having a hard time as it is, thats why they added more cache...

more cores would probably need a new imc design, and they either cant or dont want to do this... they probably thought that going for 3 channels would be tricky, and instead they go for quad channels with MCM 12-16core chips, just doubling the imc instead of reworking it.

i wonder how many extra cores they could add if they would use a reworked imc with 3 channels, couldnt they add 2 or 4 more cores and remove cache, keeping it at the same die size?

and im curious, is it really ok to move the fpus and io directly towards the edge of the chip? cause those are some of the hottest parts of the chip, right? if those are at the far edge of the chip proper ihs bonding is really crucial, and the thermal stress on the outer rings of solder balls must be pretty high

[qcmadness]

yeah, thats what i wondered as well... my guess is that the imc wouldnt be able to feed more than 8 cores, and its already having a hard time as it is, thats why they added more cache...

more cores would probably need a new imc design, and they either cant or dont want to do this... they probably thought that going for 3 channels would be tricky, and instead they go for quad channels with MCM 12-16core chips, just doubling the imc instead of reworking it.

They could only manage to add 1 more module (total 5) in 2012's BD's refresh...

[saaya]

They could only manage to add 1 more module (total 5) in 2012's BD's refresh...

to make it 5 cores? 0_o

[FlanK3r]

saya: basic point Bulldozers are modules, one module has 2 cores and shared L2.

[-Boris-]

saya: basic point Bulldozers are modules, one module has 2 cores and shared L2.

But he do has a point. 5 units, call them modules or cores, will make an odd looking chip.

[saaya]

uhmmm how do you define core?
core as in complete core with fp and integer, or core as in integer?

right now amd calls something 2 cores which is actually only one core but with 2 integer pipes, no?
intel could do the same and cool a single core with ht support 2 cores... but they dont cause its misleading...

[Oliverda]

uhmmm how do you define core?
core as in complete core with fp and integer, or core as in integer?

right now amd calls something 2 cores which is actually only one core but with 2 integer pipes, no?
intel could do the same and cool a single core with ht support 2 cores... but they dont cause its misleading...

The core itself gets a new definition with CMT.

Btw don't forget that the Conroe/Penryn has a pretty large area which has been shared between two cores. It is the L2 cache.

[Opteron146]

Hans, be sure to look me up about the time we are launching it so that we can make sure you have all of the final data.

It will be Q3 when you are launching your server parts .. I sincerely hope Hans will get the "final data" already in Q2 with Zambezi's launch. Or are you going to switch departments in Q2 ? ;-)))

To me this all looks backwards now. All the cache eats many times the core size, which made me wondering. Wouldn't it be more useful to ditch half of those caches and use the transistors to make the actual cores a lot beefier?

You mean beefy like in the sense that you would have to ask your hyperthreaded friend to help you eating up the bloody, beefy steak, because otherwise you wouldn't be able to swallow it alone ? No good idea ... because that just would leave you fighting for the beefiest pieces and in the end you would end up still being hungry, because one big steak is still too small to feed 2 beefy guys .. no good idea at all
Furthermore, the biggest car engine is useless without fuel ... think about data as fuel and Caches as fuel tank and RAM memory as gas stations (because it is comparatively quite far away ;-)).

more cores would probably need a new imc design, and they either cant or dont want to do this... they probably thought that going for 3 channels would be tricky, and instead they go for quad channels with MCM 12-16core chips, just doubling the imc instead of reworking it.

Actually ... the BD's IMC is new:

and Triple channel ist due in 2012 with the next gen bulldozers. At least for servers .. no clue about desktops. The new chips will have PCIe links, too, thus they might be compatible to Llano's Fusion socket. Other possibility would be a socket 1366/1356 competitor, e.g. a socket AM3++ with Triple channel for enthusiast. Not sure if that market would be big enough for AMD, though.

i wonder how many extra cores they could add if they would use a reworked imc with 3 channels, couldnt they add 2 or 4 more cores and remove cache, keeping it at the same die size?

1 module = 2 Cores more plus PCIe. That has to be enough .. it will be around Thuban's die size, probably bigger .. not cheap to produce something like that.
BUT: Desktop users will get a 4 module version (Komodo), 5 modules are for servers, only (Sepang).

and im curious, is it really ok to move the fpus and io directly towards the edge of the chip? cause those are some of the hottest parts of the chip, right? if those are at the far edge of the chip proper ihs bonding is really crucial, and the thermal stress on the outer rings of solder balls must be pretty high

The other solution would be to let them face the center of the whole die ... so you think that would be a better idea to let 4 FPUs heat up the die's center ? ;-)

They could only manage to add 1 more module (total 5) in 2012's BD's refresh...

Yes, but only for servers, see above.

@Hans:
Can you identify the blocks left of the decoders ? BTBs / ITLBs / something else ?


Thanks

[-Boris-]

uhmmm how do you define core?
core as in complete core with fp and integer, or core as in integer?

right now amd calls something 2 cores which is actually only one core but with 2 integer pipes, no?
intel could do the same and cool a single core with ht support 2 cores... but they dont cause its misleading...

So, my old computer without dedicated fpu is a halfcore or coreless? You don't need a FPU to build a core.

[FlanK3r]

maybe with refresh Komodo will really 5/6 modules to desktop (again IB from Intel)

[Dresdenboy]

Many thanks, Hans! Nice work!

The SRAMs in the lower left corner of the module look very similar to the branch prediction SRAMs in the K8L core.

To me this all looks backwards now. All the cache eats many times the core size, which made me wondering. Wouldn't it be more useful to ditch half of those caches and use the transistors to make the actual cores a lot beefier?

The caches decouple the cores from the slow DRAMs. The faster the cores the more important the caches. They provide both more bandwidth and lower latency. I already had a lengthy discussion about IPC in the comments section of one blog entry here:
http://citavia.blog.de/2010/10/26/mo...436/#c14405664

There is a formula for calculating IPC:

IPC = 1/(1/I + BP + IC + DC)
I=average sustained issue rate (depending on code mix for BD - more FP, more Int?)
BP=average branch prediction penalty in cycles (calculated as percentage of branches * misprediction rate * cycles per misprediction)
IC=average instruction cache miss rate in cycles
DC1=average L1 data cache miss rate in cycles (calculated like avg. branch pred. penalty)
DC2=average L2 data cache miss rate in cycles (dito)

Insert your numbers and miss rates and watch the effects.

Or think it this way: if 1MB more L2 (~6mm^2) buys you 10% higher average (!) IPC for a fraction of the power you need to use in the core (and a few mm^2) to achieve the same - which of those options would you choose?

See this review comparing - besides other CPUs - a 2.8GHz 2C PhII (downclocked) with 512kB L2 per core and 6MB L3 (for 2 cores!) and a 2.8GHz 2C AthII with 1MB L2 per core and no L3:
http://www.techpowerup.com/reviews/A..._X2_240/4.html
In several benchmarks the AthII is faster.

[saaya]

so one ctm core is now two cores... cause amd says so...?

You mean beefy like in the sense that you would have to ask your hyperthreaded friend to help you eating up the bloody, beefy steak, because otherwise you wouldn't be able to swallow it alone ? No good idea ... because that just would leave you fighting for the beefiest pieces and in the end you would end up still being hungry, because one big steak is still too small to feed 2 beefy guys .. no good idea at all
Furthermore, the biggest car engine is useless without fuel ... think about data as fuel and Caches as fuel tank and RAM memory as gas stations (because it is comparatively quite far away ;-)).

i dont think he had any particular method of boosting performance in mind, but with more space used for cache than cores, isnt there a lot you COULD do if you would cut down on the cache?

Actually ... the BD's IMC is new:

hmmm well 1333 to 1600 is a 25% boost, so only a 20% bandwidth boost sounds weird, and a 30% "memory performance" boost doesnt sound very impressive... to me it looks like an updated version, not even tweaked a lot just some stuff added and then clocked higher... which isnt impressive seeing as current imcs can already do 2000,,, but ok, we will see...

Other possibility would be a socket 1366/1356 competitor, e.g. a socket AM3++ with Triple channel for enthusiast. Not sure if that market would be big enough for AMD, though.

of course not... thats why you dont do a platform for ocers but recycle one like intel did...

The other solution would be to let them face the center of the whole die ... so you think that would be a better idea to let 4 FPUs heat up the die's center ? ;-)

of course not, but isnt there something in between? at the edge is good, but right at the edge... im just saying after reading about all that whisker stuff and thermal stress on solder balls with memory chips (worked for a module house) it looks like a possible problem to me... especially thinking of nvidias bumpgate disaster in the past few years...

thx!

So, my old computer without dedicated fpu is a halfcore or coreless? You don't need a FPU to build a core.

come on, your just splitting hairs :P a core without an fpu wont be able to run most of the code current day cores spend most of their time digesting :P

so if you ask me, yes, a core for a desktop/server without an fpu in 2010+ isnt really a core...

just because one block can process several chunks of data at the same time it doesnt make it a multi core... at least if you ask me...
thats just misleading... i mean cpus can load and store at the same time now, even have multiple ls units, so what, they are already multi core then? :P

[FlanK3r]

but Zambezi will be 1866 MHz DDR3 support (1600 is for Interlagos)

[Dimitriman]

Saaya the server BD will accomodate standard ddr3 1600 while desktop will actually suppor ddr3 1866 which in dual channel will provide over 29 gb/s bandwidth. Thats more than the tripple channel socket 1366 b/w of 25 gb/s while using its dd3 1066 officially suppported.

source: http://www.techpowerup.com/134739/AM...-Revealed.html

[informal]

Saaya,each BD Module has two full cores,each having dedicated integer pipelines and can have either 1(per core) 128bit FMAC or 256bit FMAC,depending on the workload(single or multithreaded).So you see,the cores are not half as*ed and crippled in any way,you have everything that traditional core has plus more if you run single threaded workloads(2x FP throughput with ability to execute 2 FADDs or 2 FMULs in parallel,which is not possible today per single core,in any x86 core).Shared frontend is actually a good thing,being able to make the best use of fetch bandwidth available in either of the workloads scenarios (I bet this is the key component of the effectiveness of this design,apart from the schedulers of course).

As for memory,BD desktop officially supports 1866 standard,so one can assume it will unofficially be able to run with RAM modules clocked much higher than that.Add on top of that a 30% IMC throughput improvement,without adding a 3rd channel,and you get a massively stronger memory throughput,which is needed with 8 stronger than Thuban cores .

[JF-AMD]

To me this all looks backwards now. All the cache eats many times the core size, which made me wondering. Wouldn't it be more useful to ditch half of those caches and use the transistors to make the actual cores a lot beefier?

Actually the cores are beefy enough. the engineering team did a very good job of balancing the cache to core to die ratios to optimize for performance.

yeah, thats what i wondered as well... my guess is that the imc wouldnt be able to feed more than 8 cores, and its already having a hard time as it is, thats why they added more cache...

You sure spend a lot of time complaining about AMD. If you are so sure that our products are a flop, why bother?

As for the memory controller, it will have no problem feeding the cores. AMD has a long history of high performing memory controllers, you should look at the legacy of products that we have delivered to market. Then look at the fact that we are giving a 50% increase in throughput. The combination of those two alone are 2 great pieces of evidence that the memory controller will be just fine. You have no basis for your statement other than the desire to see AMD fail.

As to the caches, weren't all of the intel fanboys raving about intel's cache siszes in the past and saying that AMD caches were too small? You can't have it both ways.

right now amd calls something 2 cores which is actually only one core but with 2 integer pipes, no?
intel could do the same and cool a single core with ht support 2 cores... but they dont cause its misleading...

Actually a core is a single set of integer execution pipelines. AMD has one per core, intel has one per core. I have trouble seeing your argument.

The problem with HT is that while it doubles the number of threads that you can handle, it does not double the number of integer execution pipelines, or, more importantly the number of schedulers. If you have only one scheduler and only one pipeline, calling to two cores would really be misleading.

Each bulldozer module has 2 integer schedulers and 2 sets of integer pipelines, which is why it is defined as 2 cores. This FUD is really getting tiring.

So, my old computer without dedicated fpu is a halfcore or coreless? You don't need a FPU to build a core.

Exactly. Plus, we have 1 FPU per core. We can combine them to get to 256-bit AVX. Intel combines a 128-bit FPU and the integer pipeline in order to get to 256-bit AVX. So, techincally, does that mean that Sandybridge is only a half core becasue its integer pipleine is shared with the FPU?

so one ctm core is now two cores... cause amd says so...?


hmmm well 1333 to 1600 is a 25% boost, so only a 20% bandwidth boost sounds weird, and a 30% "memory performance" boost doesnt sound very impressive... to me it looks like an updated version, not even tweaked a lot just some stuff added and then clocked higher... which isnt impressive seeing as current imcs can already do 2000,,, but ok, we will see...

so if you ask me, yes, a core for a desktop/server without an fpu in 2010+ isnt really a core...

1. Everyone but you is seems to be OK with this.
2. Clock speed percentage rarely equals actual throughput percentage. I can't believe that you don't know that.
3. Every single Bulldozer core has an FPU. 16 cores, 16 FPUs. Spreading lies like you are is not helping your credibility.

[flyck]

hmmm well 1333 to 1600 is a 25% boost

1600-1333 = 267

267/1333 = 0.20030007

so to me this is 20% ?

[zalbard]

1600-1333 = 267

267/1333 = 0.20030007

so to me this is 20% ?

You're absolutely correct.
I believe the biggest memory performance boost will come from lower latency thanks to the improved IMC, though.