Intel plans to deliberately limit Sandy Bridge overclocking

[Hornet331]

Yep, enthusiasts have always been talking about upcoming products, mostly for exchanging ideas and getting prepared for the future. But I've noticed a disturbing new trend lately, it seams to be the new kind of physiological warfare that starts with some known propaganda sites, and keeps going by few known people in this forum (and other forums too).

The purpose seams not to be learning and exchanging ideas about upcoming products any longer, it is more about speculating on the negative sides and bashing a product before it gets out.

In my opinion this new trend has started by a few ATi-PR-agents, but apparently the effect was good, and now we see AMD-PR-agents are using the same kind of propaganda too.

*cough* AEG, Nvidia, first *cough*

Thought I give it to you that there might be still some "undercover" reps (from multiple companies) posting here without outing themself for whom they work. (nedjo was the last one, but he got exposed )

[Metroid]

I have heard this just before Nehalen was launched. I believe when I see it. Probably this is just another crapload created.

[Sentential]

Ok so let me get this straight another thread talking about how intel is planning on killing overclocking? mmmmhmm

Intel: Lol we're intel and overclocking is bad
<AMD Releases Black Edition chips that sell better than non BE>
Intel: Lol jk we really do like overclocking see look at our K and QX series chips! See we want your money too!

[terrace215]

AMD HAS their act together; they're on track for future CPUs and GPUs

Except for the GloFo 32nm process needed for Llano & Bulldozer, which has already officially delayed Llano...

[informal]

Delay of couple of months is nothing alarming.By the time Q1 comes and Llano launches,all the quirks would be ironed out and BD will have a solid node to flower on

[BeepBeep2]

AMD HAS their act together; they're on track for future CPUs and GPUs and performance is pretty darn good for the price-points. I don't care to see $1000+ CPU's, but it's the tech from the high-end that is scaled down. About the only way AMD could make MORE money is if they drop prices again, or if they release an 8-core AM3 processor and sell it as, for example, a Phenom II FX chip.

That could be very possible under 32nm me thinks, but 45nm may not meet power requirements/overclocking capability.

[informal]

Yeah Beep,Bulldozer is/will be 8 cores,32nm,BE/unlocked and AM3 compatible.It all fits .

[Manicdan]

That could be very possible under 32nm me thinks, but 45nm may not meet power requirements/overclocking capability.

they have 12 cores for server chips, sure its low 2ghz, but still its very possible for them to do FX style chips if they wanted.

[Drwho?]

Albert Einstein said "Make everything as simple as possible, but not simpler" , so, I am going to say it as simple as I can, and you guys can quote me to reply to those silly stuffs:
"Overclocking will be different on SB, but it will still be a lot of fun too, and it will be as good/high as usual, and Anybody who claim the opposite just have an agenda"

Sorry for not sharing my results ... hehehe ... but well, you guys are slow on your SuperPi results and so on .... hahahahahaha

Drwho?

[Manicdan]

Overclocking will be different on SB

Drwho?

can you give us any specifics? or is that all under NDA

[Chumbucket843]

I wonder about the relation between the max OC and SB's SSE units,since it looks like intel opted for double pumping the SSE units(hinted by almost equal die are for one SB core and one Westmere core,meaning units are not physically extended like before,but more likely double pumped).

they did not double pump anything in SB and it's core size is larger than westmere's by a considerable amount.

[Drwho?]

can you give us any specifics? or is that all under NDA

I can't give details, but be aware, every performance world records will fall again ... you 'll get plenty of Ghz!

DrWho?

[informal]

they did not double pump anything in SB and it's core size is larger than westmere's by a considerable amount.

No it's not... take a look yourself:
http://citavia.blog.de/2010/04/14/a-...no-2x-8371390/



If you consider the 1.2mm2 "a considerable amount",then you are correct sir.
The SSE part of the core has changed negligibly .Where is the widened(256bit) SSE logic?How did it fit inside the same die area?

[qcmadness]

I wonder about the relation between the max OC and SB's SSE units,since it looks like intel opted for double pumping the SSE units(hinted by almost equal die are for one SB core and one Westmere core,meaning units are not physically extended like before,but more likely double pumped).

SB has AVX, which may do 1 256-bit SSE instruction or may fuse 2 128-bit SSE instructions into 1 256-bit instruction.

[informal]

SB has AVX, which may do 1 256-bit SSE instruction or may fuse 2 128-bit SSE instructions into 1 256-bit instruction.

We all know SB has AVX,it's been known for a while... We do not know how they managed the increased throughput with no die area investment(hence the double pumped proposition).

edit: Also,the thread title is a bit misleading,intel didn't do this deliberately ,it's just the part of the design.It's not like they made it this way just for the sake of preventing people from OCing these chips.

[Solus Corvus]

Well it's good to hear that there will be some nice overclocking with these chips. Lowend Intel chips have been favorite budget clockers of mine for quite a while. There are a few of my highly overclocked celerons running reliably to this day in people's desktops.

Will overclocking be unlimited for all chips and not just unlocked ones?

[terrace215]

Delay of couple of months is nothing alarming.By the time Q1 comes and Llano launches,all the quirks would be ironed out and BD will have a solid node to flower on

Llano ain't launching in Q1. Ontario is.

As of now, all that is promised for Llano is shipments (of CPUs NOT systems) in H1. If things get back on track, you might see a Q2 launch, if not, Q3+.

And you don't disclose a mere "quirk" publicly after posting a decent financial quarter-- it's gotta be bad if they feel they must disclose it now, despite the effect they know that disclosure will have on the analysts & investors & potential customers.

[qcmadness]

We all know SB has AVX,it's been known for a while... We do not know how they managed the increased throughput with no die area investment(hence the double pumped proposition).

edit: Also,the thread title is a bit misleading,intel didn't do this deliberately ,it's just the part of the design.It's not like they made it this way just for the sake of preventing people from OCing these chips.

we have got around 10% more transistor in SB, which should mostly about AVX.
Apart from AVX, I have not heard of any major improvement than Westmere / Nehalem.

[Drwho?]

We all know SB has AVX,it's been known for a while... We do not know how they managed the increased throughput with no die area investment(hence the double pumped proposition).

edit: Also,the thread title is a bit misleading,intel didn't do this deliberately ,it's just the part of the design.It's not like they made it this way just for the sake of preventing people from OCing these chips.

The AMD architects wish that I would answer this question here ... hahahaha ... no way! the poker game face is ON !

[qcmadness]

Llano ain't launching in Q1. Ontario is.

As of now, all that is promised for Llano is shipments (of CPUs NOT systems) in H1. If things get back on track, you might see a Q2 launch, if not, Q3+.

Launch =/= shipment

NVIDIA launched GTX480 / GTX470 in March, and shipped in April.

[OhNoes!]

We all know SB has AVX,it's been known for a while... We do not know how they managed the increased throughput with no die area investment(hence the double pumped proposition).

edit: Also,the thread title is a bit misleading,intel didn't do this deliberately ,it's just the part of the design.It's not like they made it this way just for the sake of preventing people from OCing these chips.

Not to mention a tautology, as "plan" already implies premeditation and deliberateness, but I guess we have to spice it up a little huh, OP?

@ Informal, it's good to see a series of objective posts from you in the last few days. I was beginning to get worried, a little.

[-Sweeper_]

Llano ain't launching in Q1. Ontario is.

As of now, all that is promised for Llano is shipments (of CPUs NOT systems) in H1. If things get back on track, you might see a Q2 launch, if not, Q3+.

And you don't disclose a mere "quirk" publicly after posting a decent financial quarter-- it's gotta be bad if they feel they must disclose it now, despite the effect they know that disclosure will have on the analysts & investors.

dont be so cruel, let him believe everything is rosy

[informal]

Llano ain't launching in Q1. Ontario is.

As of now, all that is promised for Llano is shipments (of CPUs NOT systems) in H1. If things get back on track, you might see a Q2 launch, if not, Q3+.

Let's round up Llano to Q4 and BD to 2012 Q2 or even Q3,just to be on the safe side.And then when they launch next year we can say AMD hugely over delivered

[Solus Corvus]

Yeah, let's all start talking about AMD.

[Hornet331]

No it's not... take a look yourself:
http://citavia.blog.de/2010/04/14/a-...no-2x-8371390/

If you consider the 1.2mm2 "a considerable amount",then you are correct sir.
The SSE part of the core has changed negligibly .Where is the widened(256bit) SSE logic?How did it fit inside the same die area?

Hmm theres something wrong with that picture, cause it lsts SB with 2mb, yet its either 1.5mb or 2.5mb l3 per core.