I suppose than that is referred to commands communication bewthem the CPU and GPU, basically, when the CPU tells the GPU what to do. When that its happening, it should not use the IMC, HyperTransport, or anything, because it is on the same piece of silicon. However, when the GPU is going to request the bulk of the data, you are going to access its VRAM (Shared in the RAM) anyways, so you are basically cutting the CPU-to-GPU coordination latency. Not having to use external bus at all means that it should have a sort of huge Cache or buffers to store tons of info to not have to actually access the external bus, or that the CPU uploads data to process to the GPU in real time instead of storing it on VRAM then telling the GPU to go to retrieve it.
In current platforms topology works like this:

_Northbridge IGP without Sideport (Shared RAM): CPU uploads graphics data to the shared RAM at one hop using the IMC, and also commands the GPU one hop away using HyperTransport. The IGP has to travel two hops, using HyperTransport then the CPU IMC to retrieve the data.
_Northbridge IGP with Sideport (Exclusive): CPU uploads data to the exclusive IGP VRAM that is two hops away, using HyperTranport to the Northbridge then the mini IMC that it should have to manage the Sideport. It still commands the GPU one hop away, and the GPU got its VRAM one hop away, too.
_Northbridge IGP with Sideport AND shared RAM: You're using as VRAM both the Sideport and some shared RAM, this means that you should have an extra overhead. The topology should be depending on where the CPU is uploading to what part of the VRAM and where the GPU is retrieving it, but basically is the last two simultaneously.
_PCIe Video Card: GPU is two hops away from the CPU (HyperTransport to Northbridge, then PCIe Bus to Video Card), and the VRAM is at three (Using the GPU IMC). Nuff' said.
_PCIe Video Card with TurboCache/HyperMemory: Similar to the Northbridge IGP with Sideport AND shared RAM, as the GPU also got some VRAM of its own, just that the GPU is two hops away (HyperTransport, PCIe Bus), its exclusive VRAM at three (Add GPU IMC to the previous path), the shared one at one hop (Using the GPU IMC) from the CPU, but three from the GPU (PCIe, Hyper Transport, Processor IMC). But the concept is the same.
_Fusion: CPU commands GPU internally, lowest possible latency at 0 hops. You are using shared RAM at just one hop with the IMC, so whatever either the CPU or GPU wants to access must have to do it though the same bus. Possibily, the most important improvement would be that data to process is directly uploaded from the CPU to GPU in real time instead of it just saying it where in the RAM it has placed it at, in what case it would have to retrieve it from the VRAM.