Its getting close now. Ill just quote a post from S|A since its easier.

Fusion, comming soon:http://sites.amd.com/us/fusion/apu/P...ion.aspxFusion,

whitepaper:http://sites.amd.com/us/Documents/48...epaper_WEB.pdfA bit about system bus and memory controler: Quote: The key aspect to note is that all the major system elements – x86 cores, vector (SIMD) engines, and a Unifed Video Decoder (UVD) for HD decoding tasks – attach directly to the same high speed bus, and thus to the main system memory. This design concept eliminates one of the fundamental constraints that limits the performance of traditional integrated graphics controllers (IGPs). and ... Quote: Although the APU’s scalar x86 cod SIMD engines share a common path to system memory, AMD’s frst generation implementations divide that memory into regions managed by the operating system running on the x86 cores and other regions managed by software running on the SIMD engines. AMD provides high speed block transfer engines that move data between the x86 and SIMD memory partitions. Unlike transfers between an external frame buffer and system memory, these transfers never hit the system’s external bus. Clever software developers can overlap the loading and unloading of blocks in the SIMD memory with execution involving data in other blocks. Insight 64 anticipates that future APU architectures will evolve towards a more seamless memory management model that allows even higher levels of balanced performance scaling.