old-school die shrink (250nm->180nm)Originally Posted by Sn0wm@n
- same equipment, same fab, same lasers, same 200mm wafers
- most transistor parameters same or linear scale. Same materials.
- no need for special techniques, no significant sub-micron effects
die shrink (ie 45nm->32nm)
- new never before used techniques: liquid immersion, double patterning, soon UV and hyper index lens
- huge changes to materials: different insulation between metal layers, different via plugs, copper for connectors, metal instead of polysilicon for gate, straining of silicon using doping to improve carrier mobility
- drastic changes to transistor parameters. Because of sub-micron effects, instead of about a dozen, now hundreds of parameters to precisely control.
- previously negligible effects like gate dielectric leakage have HUGE effects on power/heat.
New smaller process means smaller dies so more per wafer. At first yields are poor, so definetly costs more. But, once yields mature, the higher cost per wafer is recovered and more.
If they could, silicon companies would avoid die shrinks. Nobody likes risks, delays or higher costs. But, its a necessity.
You can make an Athlon core on 250nm. But, you can't do that with much larger designs like 5870 or Nehalem. Dies would be enormous. Likewise with power.
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EDIT: just cores
P3 Slot1 250nm "Katmai" - 9 million transistors, 5 layer
Athlon SlotA 250nm - 22 million transistors, 6 layer
constrast/compare:
Nehalem 45nm 730 million (probably ~300/4 = 75 million per core)
G200 55nm 1400 million
Fermi 40nm 3200 million
future: slowdown.. limit on growth #cores, die size, power output.. for certain clock race is long over.
IMHO: after 2010, I don't think AMD and nVidia will be doubling transistor count anymore. Will be interesting what they come up with to sell chips... maybe AMD more L2 cache and/or faster bus stalling strategy?
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