The Fermi Thread - Part 3

[LordEC911]

lol agreed, you wonder if the peeps in this forum where in charge we would have had any problems at all with the yield on Fermi silicon

We wouldn't have any yield problems... the chip would never make it to the Fab since the simulations would keep telling us it won't work.

[Sushi Warrior]

Depends on the salvage part...
Correct with the TSMC contract, we don't know anything about either contracts, though I suspect AMD/ATi has been getting a decent discount as well over the last few years.
I also highly doubt Nvidia is seeing 60% yields right now...


40nm wafers are more expensive than 65/55nm wafers...
Lower binned GDDR5? It is clocked slower but I don't think it is a lower bin.

40nm should be cheaper, they pay roughly the same price per wafer but get many more chips.
And lower clocked DDR5 is cheaper, obviously.... and I don't know why they would use fast DDR5 and downclock it (if that is what you are implying).

[Vardant]

Correct with the TSMC contract, we don't know anything about either contracts, though I suspect AMD/ATi has been getting a decent discount as well over the last few years.

I just quickly googled and over the past years, NV has been the biggest or among the biggest customers.
If I was in TSMC's position, I would be trying to keep NV on my good side no matter what. ATI will eventually move to GloFo, but NV doesn't have to. And you don't want to lose two of your biggest customers, that's for sure.

Or maybe I'm completely wrong, it's just fun to speculate sometimes

[highoctane]

40nm wafers are more expensive than 65/55nm wafers...

Ok, how much more .01, $10, $100, or maybe $200000?? I mean we can assume costs are what we want to imagine them to be unless somebody slipped the invoices out to somebody who leaked real cost its all assumed.

Lower binned GDDR5? It is clocked slower but I don't think it is a lower bin.

I can "think" its binned lower and is cheaper, same logic being used...

Until somebody posts what vram is used what basis of comparison is there without a spec sheet at the least.

We can both assume the other is wrong but that doesn't make either of us right.

I don't know how many times the bom cost argument has gone on about Nvidia loosing money on gpus only to see solid financial statements to the contrary.

[Chumbucket843]

Common sense maybe?

Larger die = more expensive
Larger memory interface = higher complexity PCB = more expensive
Higher TDP = higher complexity PCB, better/more power components, larger heatsink = more expensive
More memory = more expensive

I said it before... GF100 will cost Nvidia more than ~2x to make than Cypress and that is being conservative.

maybe not common sense. i cant tell you how much bom is and i have common sense.

tdp is 30% more and heatsink is not larger than 5870. they hire companies for good thermal solutions which helps when you have a power hungry card.

vram isnt a huge portion of costs on high end cards unless you use top bin ic's.

maybe you could show me some information on the cost from a research firm. im not paying for that. even if gf100 isnt profitable its not a big deal. high end and ultra high end is more about reputation than profitability.

[Sn0wm@n]

40nm should be cheaper, they pay roughly the same price per wafer but get many more chips.
And lower clocked DDR5 is cheaper, obviously.... and I don't know why they would use fast DDR5 and downclock it (if that is what you are implying).

more complex lithography equipment = cheaper to you ????



your a pro @ the silicon business

[LordEC911]

40nm should be cheaper, they pay roughly the same price per wafer but get many more chips.
And lower clocked DDR5 is cheaper, obviously.... and I don't know why they would use fast DDR5 and downclock it (if that is what you are implying).

Nope, they pay more for the newer wafers.

I just quickly googled and over the past years, NV has been the biggest or among the biggest customers.
If I was in TSMC's position, I would be trying to keep NV on my good side no matter what. ATI will eventually move to GloFo, but NV doesn't have to. And you don't want to lose two of your biggest customers, that's for sure.

Or maybe I'm completely wrong, it's just fun to speculate sometimes

The difference is, Nvidia uses the node once it is mature and have a high volume. AMD/ATi has a lower volume but hops onto the node as early as possible and helps develop it. I'm sure each company gets discounts based on their involvement.

Ok, how much more .01, $10, $100, or maybe $200000?? I mean we can assume costs are what we want to imagine them to be unless somebody slipped the invoices out to somebody who leaked real cost its all assumed.

I don't know how many times the bom cost argument has gone on about Nvidia loosing money on gpus only to see solid financial statements to the contrary.

A few thousand more.
Too bad financials aren't broken down per SKU...
BOM for a single product |= profitability for the entire company.

maybe not common sense. i cant tell you how much bom is and i have common sense.

tdp is 30% more and heatsink is not larger than 5870. they hire companies for good thermal solutions which helps when you have a power hungry card.

vram isnt a huge portion of costs on high end cards unless you use top bin ic's.

maybe you could show me some information on the cost from a research firm. im not paying for that. even if gf100 isnt profitable its not a big deal. high end and ultra high end is more about reputation than profitability.

So you don't think the GTX480 heatsink costs more than the 5870's?

I have posted the info from a research firm before, I will see if I can find it again.

[insurgent]

High-end means high-end, not TOP-end/bleeding edge. GTX480 is a high-end product. So is a GTX 280, Radeon 5870, and GTX 295, frankly.

I agree with GT, also I always thought of it as price brackets, not based on performance. An average consumer won't be buying a $500US card because of the price, I think that means it's high end.

A few more days left, man I hope they drive down prices.

[highoctane]

A few thousand more

Ok based on what, a few is that two thousand or four thousand more...

I mean its really just silly to just throw out ambiguous numbers that anybody here can here can do with no real substance behind it, at least post something solid to back it up.

I mean ATI and Nvidia are going to pay a few thousand more for their electric this month, lawn maintenance is going to be a few hundred more and tsmc is going to be billing them a few thousand more this month as well, just believe me...

[***Deimos***]

more complex lithography equipment = cheaper to you ????

your a pro @ the silicon business

old-school die shrink (250nm->180nm)
- same equipment, same fab, same lasers, same 200mm wafers
- most transistor parameters same or linear scale. Same materials.
- no need for special techniques, no significant sub-micron effects

die shrink (ie 45nm->32nm)
- new never before used techniques: liquid immersion, double patterning, soon UV and hyper index lens
- huge changes to materials: different insulation between metal layers, different via plugs, copper for connectors, metal instead of polysilicon for gate, straining of silicon using doping to improve carrier mobility
- drastic changes to transistor parameters. Because of sub-micron effects, instead of about a dozen, now hundreds of parameters to precisely control.
- previously negligible effects like gate dielectric leakage have HUGE effects on power/heat.

New smaller process means smaller dies so more per wafer. At first yields are poor, so definetly costs more. But, once yields mature, the higher cost per wafer is recovered and more.

If they could, silicon companies would avoid die shrinks. Nobody likes risks, delays or higher costs. But, its a necessity.

You can make an Athlon core on 250nm. But, you can't do that with much larger designs like 5870 or Nehalem. Dies would be enormous. Likewise with power.

=================

EDIT: just cores
P3 Slot1 250nm "Katmai" - 9 million transistors, 5 layer
Athlon SlotA 250nm - 22 million transistors, 6 layer

constrast/compare:
Nehalem 45nm 730 million (probably ~300/4 = 75 million per core)
G200 55nm 1400 million
Fermi 40nm 3200 million

future: slowdown.. limit on growth #cores, die size, power output.. for certain clock race is long over.
IMHO: after 2010, I don't think AMD and nVidia will be doubling transistor count anymore. Will be interesting what they come up with to sell chips... maybe AMD more L2 cache and/or faster bus stalling strategy?

[Sn0wm@n]

old-school die shrink (250nm->180nm)
- same equipment, same fab, same lasers, same 200mm wafers
- most transistor parameters same or linear scale. Same materials.
- no need for special techniques, no significant sub-micron effects

die shrink (ie 45nm->32nm)
- new never before used techniques: liquid immersion, double patterning, soon UV and hyper index lens
- huge changes to materials: different insulation between metal layers, different via plugs, copper for connectors, metal instead of polysilicon for gate, straining of silicon using doping to improve carrier mobility
- drastic changes to transistor parameters. Because of sub-micron effects, instead of about a dozen, now hundreds of parameters to precisely control.
- previously negligible effects like gate dielectric leakage have HUGE effects on power/heat.

New smaller process means smaller dies so more per wafer. At first yields are poor, so definetly costs more. But, once yields mature, the higher cost per wafer is recovered and more.

If they could, silicon companies would avoid die shrinks. Nobody likes risks, delays or higher costs. But, its a necessity.

You can make an Athlon core on 250nm. But, you can't do that with much larger designs like 5870 or Nehalem. Dies would be enormous. Likewise with power.

thank you for prooving my point....


btw since tsmc has to purchase new equipment thatcost more then 30 million each part who do you think pays up in the end???? amd nvidia etc.... because tsmc isnt there to please anyone except their share holder ..... so no the waffer wont cost less so the cpu will cost more .... but its up to amd nvidia etc... to have a not too big die + an easy to work arch to have the highest yield possible to recuperate on that investment .....

[Sushi Warrior]

Jeez, that's new to me, everything I have ever read before says moving to a smaller process = cheaper.... maybe I am thinking of more small shrink like 65nm to 55nm (GPU) and 65nm to 45nm (CPU)? 55nm to 40nm doesn't bring any of the real big problems with shrinkage IIRC, doesn't that only happen at 32nm and lower?

And even if the cost per wafer is higher, they get more per wafer. IF it does cost them more per wafer, I am sure the extra chips would even it all out.

I feel like I am missing something or have been horribly mis-informed.....

[FischOderAal]

It's only cheaper per core if the DIE-size decreases and as more features are integrated (=> more transistors) to increase performance this does not always happen.

[Sushi Warrior]

It's only cheaper per core if the DIE-size decreases and as more features are integrated (=> more transistors) to increase performance this does not always happen.

This is my point exactly, it seems like people are saying it would be cheaper to make Fermi (well, just the die - obvious heat issues aside) on, say, 55nm. Yes, Fermi is going to cost a fair bit to make, but does 40nm REALLY make it MORE expensive? Would a 40nm 500mm2 chip really be cheaper than a 55nm 687.5mm2 chip (assuming it scales linearly ie. 500*[55/40])?

Such a big chip is not possible for TSMC. Max size to manufacture is about 580mm².
40nm WAS necessary for GF100.

Obviously they wouldn't really make it a 55nm chip, but hypothetically speaking is it "cheaper" to make it on 55nm?

[mapel110]

Such a big chip is not possible for TSMC. Max size to manufacture is about 580mm².
40nm WAS necessary for GF100.

[weston]

whoa already 33 pages :O

still no real info, so what's the point

[Iconyu]

heres the link to the so called 'digital citizens' that where supposedly rendered from scratch, but where in fact actors in still shots animated to look like live motion, on Fermi of Course,

http://www.onesize.nl/projects/playgrounds-titles-2009

Damn I remember those pics. I remember thinking there were very photo realistic. A little too photo realistic it seems...

[mindfury]

http://www.onesize.nl/projects/playgrounds-titles-2009

It has nothing to do with Fermi.Someone just photoshoped NV logo on that screenshot.

[Sn0wm@n]

It's only cheaper per core if the DIE-size decreases and as more features are integrated (=> more transistors) to increase performance this does not always happen.

voila

whoa already 33 pages :O

still no real info, so what's the point

post count.....

propaganda


etc....

[LordEC911]

Ok based on what, a few is that two thousand or four thousand more...

I mean its really just silly to just throw out ambiguous numbers that anybody here can here can do with no real substance behind it, at least post something solid to back it up.

I mean ATI and Nvidia are going to pay a few thousand more for their electric this month, lawn maintenance is going to be a few hundred more and tsmc is going to be billing them a few thousand more this month as well, just believe me...

A few thousand dollars more per wafer adds up pretty fast when you are buying tens of thousands of wafers...

[LiquidReactor]

Is there yet any concrete evidence regarding "Fermi" GF100 die size?

I see a lot of opinions that it is going to be somewhere between G200 and G200 B3 but I have not seen any conclusive justified statements to back that up.

[LordEC911]

Is there yet any concrete evidence regarding "Fermi" GF100 die size?

I see a lot of opinions that it is going to be somewhere between G200 and G200 B3 but I have not seen any conclusive justified statements to back that up.

No pictures or anything but it will be closer to G200 than G200b.

[Sn0wm@n]

A few thousand dollars more per wafer adds up pretty fast when you are buying tens of thousands of wafers...

and thats how the foundry's of this world recuperate their cost of newer equipment

Is there yet any concrete evidence regarding "Fermi" GF100 die size?

I see a lot of opinions that it is going to be somewhere between G200 and G200 B3 but I have not seen any conclusive justified statements to back that up.

a couple pages ago there was a link to some site saying around 530 square mm dunno if its accurate tho

[highoctane]

A few thousand dollars more per wafer adds up pretty fast when you are buying tens of thousands of wafers...

General math isn't the issue, it's more or less your insistence that each wafer definitively costs "a few thousand dollars" more and how that range was derived or was it contrived.

I'm not saying you don't know but if you don't have anything to substantiate the claim what are we suppose to think. I mean I can say the wafers are more expensive but it avgs out to only $1 extra per die per wafer, I'm right trust me.

Who knows what kind of arrangement Nvidia have with TSMC and in what way wafer costs and yield issues are handled between the two. For all we know TSMC could have guaranteed price for a fixed number of operational dies regardless of the actual yield per wafer.

[LordEC911]

Who knows what kind of arrangement Nvidia have with TSMC and in what way wafer costs and yield issues are handled between the two. For all we know TSMC could have guaranteed price for a fixed number of operational dies regardless of the actual yield per wafer.

Exactly and that is why I said this...

Correct with the TSMC contract, we don't know anything about either contract,

But the original statement still stands, 40nm wafers are more expensive than 65/55nm wafers and yes, by a few thousand dollars per wafer.