The Fermi Thread - Part 3

[ElSel10]

Remember, on the GF100 architecture, ROPs, the memory controllers and L2 cache need to scale in a linear fashion to one another. ROPs come in groups of 8, L2 cache in blocks of 128KB and memory controllers in 64-bit increments.

Nope, on GF100 the ROPs are independent from the memory bus, there was a very in depth article on just this, I don't remember where it was though. Perhaps somebody can link to it?