The Fermi Thread - Part 3

[SKYMTL]

For the 448 SP GTX470, it would have 48 ROPs and 56 TMUs.

If the GTX 470 has a cut down memory interface, how would it retain the same number of ROPs?

Remember, on the GF100 architecture, ROPs, the memory controllers and L2 cache need to scale in a linear fashion to one another. ROPs come in groups of 8, L2 cache in blocks of 128KB and memory controllers in 64-bit increments.