Yoh Alien-Grey,
here is the answere from Mikeyakame about the tREF issue:
"Well about the CH1/CH2 cross clocking I don't think it has anything to do with tREF, it's to do with how aggressive the clock/ddr out mux timings are between CH1 -> MCH, CH2 -> MCH, CH1 <-> CH2 relative to the input clock/ddr signals. It's something along those lines I believe, it has to do with timing the DLL circuit delays with respect to arrival at the MCH data bus pins.
You shouldn't use a tREF of any higher than required, it might give better synthetic benchmarks, but only because you are artificially reducing the overhead on the bus by using long self-refresh periods. Normally said overhead is used for self-refreshing the data in the memory ic's while there is little bus activity, so whenever the MCH is required to fetch data out of memory, it is available to read. Otherwise if it isn't refreshing the data properly you end up introducing extra clock cycles during real world scenarios, whenever the data has to be fetched from something like the HDD".
However, I saw that the tREFs are calculated down to 2600T if I set "more relaxed" in CH1/Ch2 Clock Crossing setting.
Matter of fact that the data through put isn´t higher setting the Ch1/CH2 Clock Crossing option to "more aggressive oder aggressive".
What you gain is a little bandwidth increasing the tREFs but the higher you go with the tREFs the higher is the risk to get an instable system.
EDIT: I can´t post on the ASUS site anymore but I could rate your Tech.Points up to 15, Alien-Grey![]()




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